📄 mem_interface_top_phy_io_0.v
字号:
//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: $Name: i+IP+125372 $
// \ \ Application: MIG
// / / Filename: mem_interface_top_phy_io_0.v
// /___/ /\ Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates calibration logic, data, data strobe and the
// data mask iobs.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mem_interface_top_phy_io_0 #
(
parameter CLK_WIDTH = 1,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter DQ_BITS = 7,
parameter DQ_PER_DQS = 8,
parameter DQS_WIDTH = 9,
parameter DQS_BITS = 4,
parameter ODT_WIDTH = 1,
parameter ADDITIVE_LAT = 0,
parameter CAS_LAT = 3,
parameter ECC_ENABLE = 0,
parameter REG_ENABLE = 1,
parameter CLK_PERIOD = 5000,
parameter DDR2_ENABLE = 1,
parameter DQS_GATE_EN = 0,
parameter SIM_ONLY = 0,
parameter IDEL_HIGH_PERF = "TRUE"
)
(
input clk0,
input clk90,
input rst0,
input rst90,
input dq_oe_n,
input dqs_oe_n,
input dqs_rst_n,
input [3:0] calib_start,
input ctrl_rden,
input phy_init_rden,
input phy_init_done,
output [3:0] calib_done,
output [DQS_WIDTH-1:0] calib_rden,
input [DQ_WIDTH-1:0] wr_data_rise,
input [DQ_WIDTH-1:0] wr_data_fall,
input [(DQ_WIDTH/8)-1:0] mask_data_rise,
input [(DQ_WIDTH/8)-1:0] mask_data_fall,
output [DQ_WIDTH-1:0] rd_data_rise,
output [DQ_WIDTH-1:0] rd_data_fall,
output [CLK_WIDTH-1:0] ddr_ck,
output [CLK_WIDTH-1:0] ddr_ck_n,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq
);
// ratio of # of physical DM outputs to bytes in data bus
// may be different - e.g. if using x4 components
localparam DM_TO_BYTE_RATIO = DM_WIDTH / (DQ_WIDTH/8);
// keep CALIB_ERR internal for now
wire [3:0] calib_err;
wire [CLK_WIDTH-1:0] ddr_ck_q;
wire [DQ_WIDTH-1:0] dlyce_dq;
wire [DQ_WIDTH-1:0] dlyinc_dq;
wire [DQ_WIDTH-1:0] dlyrst_dq;
wire [DQS_WIDTH-1:0] dlyce_dqs;
wire [DQS_WIDTH-1:0] dlyinc_dqs;
wire dlyrst_dqs;
wire [DQS_WIDTH-1:0] delayed_dqs;
// following signals used only if DQS gate is supported
wire [DQS_WIDTH-1:0] dlyce_gate;
wire [DQS_WIDTH-1:0] dlyinc_gate;
wire [DQS_WIDTH-1:0] dlyrst_gate;
wire dlyrst_dq_gate;
wire [DQS_WIDTH-1:0] gate_dqs;
wire [DQS_WIDTH-1:0] gate_clr;
//***************************************************************************
generate
if (!DQS_GATE_EN) begin: gen_phy_calib
// if no DQS gate
mem_interface_top_phy_calib_0 #
(
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.ECC_ENABLE (ECC_ENABLE),
.REG_ENABLE (REG_ENABLE),
.CAS_LAT (CAS_LAT),
.SIM_ONLY (SIM_ONLY),
.CLK_PERIOD (CLK_PERIOD)
)
u_phy_calib_0
(
.clk0 (clk0),
.clk90 (clk90),
.rst90 (rst90),
.calib_start_0 (calib_start),
.ctrl_rden_0 (ctrl_rden),
.phy_init_rden_0 (phy_init_rden),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.calib_done_0 (calib_done),
.calib_rden (calib_rden),
.dlyrst_dq (dlyrst_dq),
.dlyce_dq (dlyce_dq),
.dlyinc_dq (dlyinc_dq),
.dlyrst_dqs (dlyrst_dqs),
.dlyce_dqs (dlyce_dqs),
.dlyinc_dqs (dlyinc_dqs)
);
end else begin: gen_phy_calib_gate
// if use DQS gating circuit
assign dlyrst_dq = {DQ_WIDTH{dlyrst_dq_gate}};
mem_interface_top_phy_calib_0 #
(
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.REG_ENABLE (REG_ENABLE)
)
u_phy_calib_0
(
.clk0 (clk0),
.clk90 (clk90),
.rst90 (rst90),
.calib_start_0 (calib_start),
.ctrl_rden_0 (ctrl_rden),
.phy_init_rden_0 (phy_init_rden),
.phy_init_done_0 (phy_init_done),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.calib_done_0 (calib_done),
.calib_err_0 (calib_err),
.calib_rden (calib_rden),
.gate_dqs (gate_dqs),
.gate_clr (gate_clr),
.dlyrst_dq (dlyrst_dq_gate),
.dlyce_dq (dlyce_dq),
.dlyinc_dq (dlyinc_dq),
.dlyrst_dqs (dlyrst_dqs),
.dlyce_dqs (dlyce_dqs),
.dlyinc_dqs (dlyinc_dqs),
.dlyrst_gate (dlyrst_gate),
.dlyce_gate (dlyce_gate),
.dlyinc_gate (dlyinc_gate)
);
end
endgenerate
//***************************************************************************
// Memory clock generation
//***************************************************************************
genvar ck_i;
generate
for(ck_i = 0; ck_i < CLK_WIDTH; ck_i = ck_i+1) begin: gen_ck
ODDR #
(
.SRTYPE ("SYNC"),
.DDR_CLK_EDGE ("OPPOSITE_EDGE")
)
u_oddr_ck_i
(
.Q (ddr_ck_q[ck_i]),
.C (clk0),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (1'b0),
.S (1'b0)
);
// Can insert ODELAY here if required
OBUFDS u_obuf_ck_i
(
.I (ddr_ck_q[ck_i]),
.O (ddr_ck[ck_i]),
.OB (ddr_ck_n[ck_i])
);
end
endgenerate
//***************************************************************************
// DQS instances
//***************************************************************************
genvar dqs_i;
generate
for(dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs
if (!DQS_GATE_EN) begin: gen_phy_dqs_iob
// if no DQS gate
mem_interface_top_phy_dqs_iob u_iob_dqs
(
.clk0 (clk0),
.clk90 (clk90),
.rst0 (rst0),
.dlyinc_dqs (dlyinc_dqs[dqs_i]),
.dlyce_dqs (dlyce_dqs[dqs_i]),
.dlyrst_dqs (dlyrst_dqs),
.dqs_oe_n (dqs_oe_n),
.dqs_rst_n (dqs_rst_n),
.ddr_dqs (ddr_dqs[dqs_i]),
.ddr_dqs_n (ddr_dqs_n[dqs_i]),
.delayed_dqs (delayed_dqs[dqs_i])
);
end else begin: gen_phy_dqs_iob_gate
// if using DQS gating circuit
mem_interface_top_phy_dqs_iob #
(
.DDR2_ENABLE (DDR2_ENABLE),
.DQS_GATE_EN (DQS_GATE_EN),
.IDEL_HIGH_PERF (IDEL_HIGH_PERF)
)
u_iob_dqs
(
.clk0 (clk0),
.clk90 (clk90),
.rst0 (rst0),
.dlyinc_dqs (dlyinc_dqs[dqs_i]),
.dlyce_dqs (dlyce_dqs[dqs_i]),
.dlyrst_dqs (dlyrst_dqs),
.dlyinc_gate (dlyinc_gate[dqs_i]),
.dlyce_gate (dlyce_gate[dqs_i]),
.dlyrst_gate (dlyrst_gate[dqs_i]),
.dqs_oe_n (dqs_oe_n),
.dqs_rst_n (dqs_rst_n),
.gate_dqs (gate_dqs[dqs_i]),
.gate_clr (gate_clr[dqs_i]),
.ddr_dqs (ddr_dqs[dqs_i]),
.ddr_dqs_n (ddr_dqs_n[dqs_i]),
.delayed_dqs (delayed_dqs[dqs_i])
);
end
end
endgenerate
//***************************************************************************
// DM instances
//***************************************************************************
genvar dm_i;
generate
for(dm_i = 0; dm_i < DM_WIDTH; dm_i = dm_i+1) begin: gen_dm
mem_interface_top_phy_dm_iob u_iob_dm
(
.clk90 (clk90),
.mask_data_rise (mask_data_rise[dm_i/DM_TO_BYTE_RATIO]),
.mask_data_fall (mask_data_fall[dm_i/DM_TO_BYTE_RATIO]),
.ddr_dm (ddr_dm[dm_i])
);
end
endgenerate
//***************************************************************************
// DQ IOB instances
//***************************************************************************
genvar dq_i;
generate
for(dq_i = 0; dq_i < DQ_WIDTH; dq_i = dq_i+1) begin: gen_dq
mem_interface_top_phy_dq_iob #
(
.IDEL_HIGH_PERF (IDEL_HIGH_PERF)
)
u_iob_dq
(
.clk90 (clk90),
.rst90 (rst90),
.dlyinc (dlyinc_dq[dq_i]),
.dlyce (dlyce_dq[dq_i]),
.dlyrst (dlyrst_dq[dq_i]),
.dq_oe_n (dq_oe_n),
.dqs (delayed_dqs[dq_i/DQ_PER_DQS]),
.wr_data_rise (wr_data_rise[dq_i]),
.wr_data_fall (wr_data_fall[dq_i]),
.rd_data_rise (rd_data_rise[dq_i]),
.rd_data_fall (rd_data_fall[dq_i]),
.ddr_dq (ddr_dq[dq_i])
);
end
endgenerate
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -