mem_interface_top_phy_write_0.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_phy_write_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Thu Aug 24 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//Reference:
//   Handles delaying various write control signals appropriately depending
//   on CAS latency, additive latency, etc. Also splits the data and mask in
//   rise and fall buses.
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_phy_write_0 #
  (
   parameter DQ_WIDTH      = 72,
   parameter ADDITIVE_LAT  = 0,
   parameter CAS_LAT       = 3,
   parameter ECC_ENABLE    = 0,
   parameter ODT_TYPE      = 0,
   parameter REG_ENABLE    = 1,
   parameter DDR2_ENABLE   = 1
   )
  (
   input                                   clk0,
   input                                   clk90,
   input [(2*DQ_WIDTH)-1:0]                wdf_data,
   input [(2*DQ_WIDTH/8)-1:0]              wdf_mask_data,
   input                                   ctrl_wren,
   input                                   phy_init_wren,
   input                                   phy_init_done,
   output                                  dq_oe_n,
   output                                  dqs_oe_n,
   output                                  dqs_rst_n,
   output                                  wdf_rden,
   output                                  odt,
   output [DQ_WIDTH-1:0]                   wr_data_rise,
   output [DQ_WIDTH-1:0]                   wr_data_fall,
   output [(DQ_WIDTH/8)-1:0]               mask_data_rise,
   output [(DQ_WIDTH/8)-1:0]               mask_data_fall
   );

  localparam MASK_WIDTH = DQ_WIDTH/8;

  // (MIN,MAX) value of WR_LATENCY for DDR1:
  //   REG_ENABLE   = (0,1)
  //   ECC_ENABLE   = (0,1)
  //   Write latency = 1
  //   Total: (1,3)
  // (MIN,MAX) value of WR_LATENCY for DDR2:
  //   REG_ENABLE   = (0,1)
  //   ECC_ENABLE   = (0,1)
  //   Write latency = ADDITIVE_CAS + CAS_LAT - 1 = (0,4) + (3,5) - 1 = (2,8)
  //     ADDITIVE_LAT = (0,4) (JEDEC79-2B)
  //     CAS_LAT      = (3,5) (JEDEC79-2B)
  //   Total: (2,10)

  localparam WR_LATENCY = (DDR2_ENABLE) ?
             (ADDITIVE_LAT + (CAS_LAT-1) + REG_ENABLE + ECC_ENABLE) :
             (1 + REG_ENABLE + ECC_ENABLE);

  wire       dq_oe_0          /* synthesis syn_maxfan = 1 */;
  reg        dq_oe_n_90_r1    /* synthesis syn_maxfan = 1 */;
  reg        dq_oe_270        /* synthesis syn_maxfan = 1 */;
  wire       dqs_oe_0         /* synthesis syn_maxfan = 1 */;
  reg        dqs_oe_n_180_r1  /* synthesis syn_maxfan = 1 */;
  reg        dqs_oe_270       /* synthesis syn_maxfan = 1 */;
  wire       dqs_rst_0        /* synthesis syn_maxfan = 1 */;
  reg        dqs_rst_n_180_r1 /* synthesis syn_maxfan = 1 */;
  reg        dqs_rst_270      /* synthesis syn_maxfan = 1 */;
  wire       odt_0;
  reg        phy_init_done_r  /* synthesis syn_preserve=1 */;
  wire       wdf_rden_0;
  reg        wdf_rden_90_r1;
  reg        wdf_rden_270;
  reg [10:0] wr_stages        /* synthesis syn_maxfan = 1 */;


  //***************************************************************************
  // Analysis of additional pipeline delays:
  //   1. dq_oe (DQ 3-state): 1 CLK90 cyc in IOB 3-state FF
  //   2. dqs_oe (DQS 3-state): 1 CLK180 cyc in IOB 3-state FF
  //   3. dqs_rst (DQS output value reset): 1 CLK180 cyc in FF + 1 CLK180 cyc
  //      in IOB DDR
  //   4. odt (ODT control): 1 CLK0 cyc in IOB FF
  //   5. write data (output two cyc after wdf_rden - output of RAMB_FIFO w/
  //      output register enabled): 2 CLK90 cyc in OSERDES
  //***************************************************************************

  // DQS 3-state must be asserted one extra clock cycle due b/c of write
  // pre- and post-amble (extra half clock cycle for each)
  assign dqs_oe_0      = wr_stages[WR_LATENCY-1] | wr_stages[WR_LATENCY];

  // same goes for ODT, need to handle both pre- and post-amble (generate
  // ODT only for DDR2)
  generate
    if (DDR2_ENABLE) begin: gen_odt_ddr2
      assign odt_0 = (ODT_TYPE != 0) ?
                     (wr_stages[WR_LATENCY-2] | wr_stages[WR_LATENCY-1]) :
                     1'b0;
    end else begin: gen_odt_ddr1
       assign odt_0 = 1'b0;
    end
  endgenerate

  assign dq_oe_0       = wr_stages[WR_LATENCY];
  assign dqs_rst_0     = ~wr_stages[WR_LATENCY-1];
  assign wdf_rden_0    = wr_stages[WR_LATENCY-1];

  // synthesis attribute equivalent_register_removal of phy_init_done_r is "no";
  always @(posedge clk0)
    phy_init_done_r <= phy_init_done;

  // first stage isn't registered
  always @(*)
    wr_stages[0] <= (phy_init_done_r) ? ctrl_wren : phy_init_wren;
  // synthesis attribute max_fanout of wr_stages is 1
  always @(posedge clk0) begin
    wr_stages[1] <= wr_stages[0];
    wr_stages[2] <= wr_stages[1];
    wr_stages[3] <= wr_stages[2];
    wr_stages[4] <= wr_stages[3];
    wr_stages[5] <= wr_stages[4];
    wr_stages[6] <= wr_stages[5];
    wr_stages[7] <= wr_stages[6];
    wr_stages[8] <= wr_stages[7];
    wr_stages[9] <= wr_stages[8];
    wr_stages[10] <= wr_stages[9];
  end

  // intermediate synchronization to CLK270
  // synthesis attribute max_fanout of  dq_oe_270 is 1
  // synthesis attribute max_fanout of  dqs_oe_270 is 1
  // synthesis attribute max_fanout of  dqs_rst_270 is 1
  always @(negedge clk90) begin
    dq_oe_270         <= dq_oe_0;
    dqs_oe_270        <= dqs_oe_0;
    dqs_rst_270       <= dqs_rst_0;
    wdf_rden_270      <= wdf_rden_0;
  end

  // synchronize DQS signals to CLK180
  // synthesis attribute max_fanout of dqs_oe_n_180_r1 is 1
  // synthesis attribute max_fanout of dqs_rst_n_180_r1 is 1
  always @(negedge clk0) begin
    dqs_oe_n_180_r1  <= ~dqs_oe_270;
    dqs_rst_n_180_r1 <= ~dqs_rst_270;
  end

  // All write data-related signals synced to CLK90
  // synthesis attribute max_fanout of dq_oe_n_90_r1 is 1
  always @(posedge clk90) begin
    dq_oe_n_90_r1  <= ~dq_oe_270;
    wdf_rden_90_r1 <= wdf_rden_270;
  end

  //***************************************************************************

  // synthesis attribute max_fanout of dq_oe_n is 1
  assign dq_oe_n   = dq_oe_n_90_r1;
 // synthesis attribute max_fanout of dqs_oe_n is 1
  assign dqs_oe_n  = dqs_oe_n_180_r1;
 // synthesis attribute max_fanout of dqs_rst_n is 1
  assign dqs_rst_n = dqs_rst_n_180_r1;
  assign odt       = odt_0;
  assign wdf_rden  = wdf_rden_90_r1;

  //***************************************************************************
  // Format write data/mask: Data is in format: {fall, rise}
  //***************************************************************************

  assign wr_data_rise = wdf_data[DQ_WIDTH-1:0];
  assign wr_data_fall = wdf_data[(2*DQ_WIDTH)-1:DQ_WIDTH];
  assign mask_data_rise = wdf_mask_data[MASK_WIDTH-1:0];
  assign mask_data_fall = wdf_mask_data[(2*MASK_WIDTH)-1:MASK_WIDTH];

endmodule