sata_hdd_vcs.v

sata_device_model,对做硬盘控制器的朋友有帮助

// generated by vcsSwiftTemplate
`timescale 1ps/1ps
module sata_hdd (
  globol_reset_n ,
  egress_data ,
  egress_fifo_status ,
  egress_data_ack ,
  egress_xfer_size ,
  egress_start_addr ,
  egress_data_req ,
  egress_fifo_rd ,
  ingress_data_ack ,
  ingress_fifo_status ,
  ingress_data ,
  ingress_fifo_wr ,
  ingress_xfer_size ,
  ingress_start_addr ,
  ingress_data_req ,
  tile0_txusrclk20_i ,
  tile0_refclkout_i ,
  tile0_rxstatus0_i ,
  tile0_rxchariscomma0_out ,
  tile0_rxcharisk0_out ,
  tile0_rxdisperr0_out ,
  tile0_rxnotintable0_out ,
  tile0_resetdone0_i ,
  tile0_rxelecidle0_out ,
  tile0_rxdata0_out ,
  tx_comreset ,
  tx_comwake ,
  txelecidle ,
  tile0_loopback0_in ,
  tile0_txdata0_in ,
  tile0_txcharisk0_in 
 );
  input globol_reset_n ;
  input [31:0] egress_data ;
  input [2:0] egress_fifo_status ;
  input egress_data_ack ;
  output [2:0] egress_xfer_size ;
  reg [2:0] egress_xfer_size__S ;
  assign egress_xfer_size = egress_xfer_size__S ;
  output [31:0] egress_start_addr ;
  reg [31:0] egress_start_addr__S ;
  assign egress_start_addr = egress_start_addr__S ;
  output egress_data_req ;
  reg egress_data_req__S ;
  assign egress_data_req = egress_data_req__S ;
  output egress_fifo_rd ;
  reg egress_fifo_rd__S ;
  assign egress_fifo_rd = egress_fifo_rd__S ;
  input ingress_data_ack ;
  input [1:0] ingress_fifo_status ;
  output [31:0] ingress_data ;
  reg [31:0] ingress_data__S ;
  assign ingress_data = ingress_data__S ;
  output ingress_fifo_wr ;
  reg ingress_fifo_wr__S ;
  assign ingress_fifo_wr = ingress_fifo_wr__S ;
  output [2:0] ingress_xfer_size ;
  reg [2:0] ingress_xfer_size__S ;
  assign ingress_xfer_size = ingress_xfer_size__S ;
  output [31:0] ingress_start_addr ;
  reg [31:0] ingress_start_addr__S ;
  assign ingress_start_addr = ingress_start_addr__S ;
  output ingress_data_req ;
  reg ingress_data_req__S ;
  assign ingress_data_req = ingress_data_req__S ;
  input tile0_txusrclk20_i ;
  input tile0_refclkout_i ;
  input [2:0] tile0_rxstatus0_i ;
  input [1:0] tile0_rxchariscomma0_out ;
  input [1:0] tile0_rxcharisk0_out ;
  input [1:0] tile0_rxdisperr0_out ;
  input [1:0] tile0_rxnotintable0_out ;
  input tile0_resetdone0_i ;
  input tile0_rxelecidle0_out ;
  input [15:0] tile0_rxdata0_out ;
  output tx_comreset ;
  reg tx_comreset__S ;
  assign tx_comreset = tx_comreset__S ;
  output tx_comwake ;
  reg tx_comwake__S ;
  assign tx_comwake = tx_comwake__S ;
  output txelecidle ;
  reg txelecidle__S ;
  assign txelecidle = txelecidle__S ;
  output [2:0] tile0_loopback0_in ;
  reg [2:0] tile0_loopback0_in__S ;
  assign tile0_loopback0_in = tile0_loopback0_in__S ;
  output [15:0] tile0_txdata0_in ;
  reg [15:0] tile0_txdata0_in__S ;
  assign tile0_txdata0_in = tile0_txdata0_in__S ;
  output [1:0] tile0_txcharisk0_in ;
  reg [1:0] tile0_txcharisk0_in__S ;
  assign tile0_txcharisk0_in = tile0_txcharisk0_in__S ;
//Generating SmartModel Windows data 

  reg [8*256:1] log$file;
  reg log$on; // 1 for log on, 0 for log off
  reg [8*256:1] cmd$str;
  reg do$model$cmd; // set to 1 to feed cmd$str             to lmc model command channel
  reg do$session$cmd; // set to 1 to feed cmd$str             to lmc session command channel

  parameter InstanceName = "";     // ** Please insert instance name here...
  parameter TimingVersion = "sata_hdd";
  parameter DelayRange = "MAX";
  parameter MC_Reference = "0000";
  initial begin
    $vcs_swift("sata_hdd",
       log$on, log$file,
       do$model$cmd, do$session$cmd, cmd$str,
       , ,
//    "attr", "InstanceName", InstanceName,    // ** and uncomment this line.
      "attr", "TimingVersion", TimingVersion,
      "attr", "DelayRange", DelayRange,
      "attr", "MC_Reference", MC_Reference,
      "in", globol_reset_n , 
      "in", egress_data , 
      "in", egress_fifo_status , 
      "in", egress_data_ack , 
      "out", egress_xfer_size , egress_xfer_size__S ,
      "out", egress_start_addr , egress_start_addr__S ,
      "out", egress_data_req , egress_data_req__S ,
      "out", egress_fifo_rd , egress_fifo_rd__S ,
      "in", ingress_data_ack , 
      "in", ingress_fifo_status , 
      "out", ingress_data , ingress_data__S ,
      "out", ingress_fifo_wr , ingress_fifo_wr__S ,
      "out", ingress_xfer_size , ingress_xfer_size__S ,
      "out", ingress_start_addr , ingress_start_addr__S ,
      "out", ingress_data_req , ingress_data_req__S ,
      "in", tile0_txusrclk20_i , 
      "in", tile0_refclkout_i , 
      "in", tile0_rxstatus0_i , 
      "in", tile0_rxchariscomma0_out , 
      "in", tile0_rxcharisk0_out , 
      "in", tile0_rxdisperr0_out , 
      "in", tile0_rxnotintable0_out , 
      "in", tile0_resetdone0_i , 
      "in", tile0_rxelecidle0_out , 
      "in", tile0_rxdata0_out , 
      "out", tx_comreset , tx_comreset__S ,
      "out", tx_comwake , tx_comwake__S ,
      "out", txelecidle , txelecidle__S ,
      "out", tile0_loopback0_in , tile0_loopback0_in__S ,
      "out", tile0_txdata0_in , tile0_txdata0_in__S ,
      "out", tile0_txcharisk0_in , tile0_txcharisk0_in__S ,
      );
  end
endmodule