mem_interface_top_phy_dq_iob.v

sata_device_model,对做硬盘控制器的朋友有帮助

//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_phy_dq_iob.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Wed Aug 16 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module places the data in the IOBs.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_phy_dq_iob #
  (
   parameter IDEL_HIGH_PERF = "TRUE"
   )
  (
   input  clk90,
   input  rst90,
   input  dlyinc,
   input  dlyce,
   input  dlyrst,
   input  dq_oe_n,
   input  dqs,
   input  wr_data_rise,
   input  wr_data_fall,
   output rd_data_rise,
   output rd_data_fall,
   inout  ddr_dq
   );

  wire    dq_in;
  wire    dq_oe_n_r;
  wire    dq_out;
  wire    iserdes_clk;
  wire    iserdes_clkb;

  // on a write, rising edge of DQS corresponds to rising edge of CLK180
  // (aka falling edge of CLK0 -> rising edge DQS). We also know:
  //  1. data must be driven 1/4 clk cycle before corresponding DQS edge
  //  2. first rising DQS edge driven on falling edge of CLK0
  //  3. rising data must be driven 1/4 cycle before falling edge of CLK0
  //  4. therefore, rising data driven on rising edge of CLK90
  ODDR #
    (
     .SRTYPE("SYNC"),
     .DDR_CLK_EDGE("SAME_EDGE")
     )
    u_oddr_dq
      (
       .Q  (dq_out),
       .C  (clk90),
       .CE (1'b1),
       .D1 (wr_data_rise),
       .D2 (wr_data_fall),
       .R  (1'b0),
       .S  (1'b0)
       );

  // make sure output is tri-state during reset (DQ_OE_N_R = 1)
  (* IOB = "TRUE" *) FDPE u_tri_state_dq
    (
     .D    (dq_oe_n),
     .PRE  (rst90),
     .C    (clk90),
     .Q    (dq_oe_n_r),
     .CE   (1'b1)
     ) /* synthesis syn_useioff = 1 */;

  IOBUF u_iobuf_dq
    (
     .I  (dq_out),
     .T  (dq_oe_n_r),
     .IO (ddr_dq),
     .O  (dq_in)
     );

  IODELAY #
    (
     .DELAY_SRC("I"),
     .IDELAY_TYPE("VARIABLE"),
     .HIGH_PERFORMANCE_MODE("TRUE"),
     .IDELAY_VALUE(0),
     .ODELAY_VALUE(0)
     )
    u_idelay_dq
      (
       .DATAOUT(dq_idelay),
       .C(clk90),
       .CE(dlyce),
       .DATAIN(),
       .IDATAIN(dq_in),
       .INC(dlyinc),
       .ODATAIN(),
       .RST(dlyrst),
       .T()
       );

  // equalize delays to avoid delta-delay issues
  assign  iserdes_clk  = dqs;
  assign  iserdes_clkb = ~dqs;

  ISERDES_NODELAY #
    (
     .BITSLIP_ENABLE("FALSE"),
     .DATA_RATE("DDR"),
     .DATA_WIDTH(4),
     .INTERFACE_TYPE("MEMORY"),
     .NUM_CE(2),
     .SERDES_MODE("MASTER")
     )
    u_iserdes_dq
      (
       .Q1           (rd_data_fall),
       .Q2           (rd_data_rise),
       .Q3           (),
       .Q4           (),
       .Q5           (),
       .Q6           (),
       .SHIFTOUT1    (),
       .SHIFTOUT2    (),
       .BITSLIP      (),
       .CE1          (1'd1),
       .CE2          (1'd1),
       .CLK          (iserdes_clk),
       .CLKB         (iserdes_clkb),
       .CLKDIV       (clk90),
       .D            (dq_idelay),
       .OCLK         (clk90),
       .RST          (rst90),
       .SHIFTIN1     (),
       .SHIFTIN2     ()
       );

endmodule