mem_interface_top_usr_ram_d_0.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_usr_ram_d_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Wed Aug 30 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   Contains the distributed RAM which stores IOB output data that is read
//   from the memory.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_usr_ram_d_0 #
  (
   parameter DATA_WIDTH = 72
   )
  (
   input [3:0]                addra,
   input [3:0]                addrb,
   input                      clka,
   input                      wea,
   input [DATA_WIDTH-1:0]     dinb,
   output [DATA_WIDTH-1:0]    douta
   );

  genvar ram16_i;
  generate
    for (ram16_i = 0; ram16_i < DATA_WIDTH;
         ram16_i = ram16_i + 1) begin: gen_ram16
      RAM16X1D u_ram16x1d
        (
         .D        (dinb[ram16_i]),
         .WE       (wea),
         .WCLK     (clka),
         .A0       (addra[0]),
         .A1       (addra[1]),
         .A2       (addra[2]),
         .A3       (addra[3]),
         .DPRA0    (addrb[0]),
         .DPRA1    (addrb[1]),
         .DPRA2    (addrb[2]),
         .DPRA3    (addrb[3]),
         .SPO      (),
         .DPO      (douta[ram16_i]));
    end
  endgenerate

endmodule