mem_interface_top_usr_top_0.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_usr_top_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Mon Aug 28 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module interfaces with the user. The user should provide the data
//   and various commands.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_usr_top_0 #
  (
   parameter BANK_WIDTH    = 3,
   parameter CS_BITS       = 0,
   parameter COL_WIDTH     = 10,
   parameter DQ_WIDTH      = 72,
   parameter DQ_PER_DQS    = 8,
   parameter DQS_WIDTH     = 9,
   parameter ROW_WIDTH     = 14
   )
  (
   input                                     clk0,
   input                                     clk90,
   input                                     rst0,
   input                                     rst90,
   input [DQ_WIDTH-1:0]                      rd_data_in_rise,
   input [DQ_WIDTH-1:0]                      rd_data_in_fall,
   input [DQS_WIDTH-1:0]                     phy_calib_rden,
   output                                    rd_data_valid,
   output [(2*DQ_WIDTH)-1:0]                 rd_data_fifo_out,
   input [2:0]                               app_af_cmd,
   input [30:0]                              app_af_addr,
   input                                     app_af_wren,
   input                                     ctrl_af_rden,
   output [1:0]                              af_conflict,
   output [2:0]                              af_cmd,
   output [30:0]                             af_addr,
   output                                    af_empty,
   output                                    app_af_afull,
   input                                     phy_init_wdf_wren,
   input [63:0]                              phy_init_wdf_data,
   input                                     app_wdf_wren,
   input [(2*DQ_WIDTH)-1:0]                  app_wdf_data,
   input [((2*DQ_WIDTH)/8)-1:0]              app_wdf_mask_data,
   input                                     wdf_rden,
   output                                    app_wdf_afull,
   output [(2*DQ_WIDTH)-1:0]                 wdf_data,
   output [((2*DQ_WIDTH)/8)-1:0]             wdf_mask_data
   );


  wire [DQ_WIDTH-1:0] i_rd_data_fifo_out_fall;
  wire [DQ_WIDTH-1:0] i_rd_data_fifo_out_rise;

  //***************************************************************************

  assign rd_data_fifo_out = {i_rd_data_fifo_out_fall,
                             i_rd_data_fifo_out_rise};

  // read FIFOs: provides minimal buffering to handle when data from different
  // DQS groups are synchronized on different clock cycles
  mem_interface_top_usr_rd_0 #
    (
     .DQ_WIDTH   (DQ_WIDTH),
     .DQ_PER_DQS (DQ_PER_DQS),
     .DQS_WIDTH  (DQS_WIDTH)
     )
    usr_rd_0
      (
       .clk              (clk90),
       .rst              (rst90),
       .rd_data_in_rise  (rd_data_in_rise),
       .rd_data_in_fall  (rd_data_in_fall),
       .ctrl_rden        (phy_calib_rden),
       .rd_data_valid    (rd_data_valid),
       .rd_data_out_rise (i_rd_data_fifo_out_rise),
       .rd_data_out_fall (i_rd_data_fifo_out_fall)
       );

  // Address/Command and Write Data FIFOs
  mem_interface_top_usr_backend_fifo_0 #
    (
     .BANK_WIDTH (BANK_WIDTH),
     .COL_WIDTH  (COL_WIDTH),
     .CS_BITS    (CS_BITS),
     .DQ_WIDTH   (DQ_WIDTH),
     .ROW_WIDTH  (ROW_WIDTH)
     )
    u_backend_fifos_0
      (
       .clk0              (clk0),
       .clk90             (clk90),
       .rst0              (rst0),
       .rst90             (rst90),
       .app_af_cmd        (app_af_cmd),
       .app_af_addr       (app_af_addr),
       .app_af_wren       (app_af_wren),
       .ctrl_af_rden      (ctrl_af_rden),
       .af_conflict       (af_conflict),
       .af_cmd            (af_cmd),
       .af_addr           (af_addr),
       .af_empty          (af_empty),
       .app_af_afull      (app_af_afull),
       .app_wdf_wren      (app_wdf_wren),
       .app_wdf_data      (app_wdf_data),
       .app_wdf_mask_data (app_wdf_mask_data),
       .phy_init_wdf_wren (phy_init_wdf_wren),
       .phy_init_wdf_data (phy_init_wdf_data),
       .wdf_rden          (wdf_rden),
       .app_wdf_afull     (app_wdf_afull),
       .wdf_data          (wdf_data),
       .wdf_mask_data     (wdf_mask_data)
       );

endmodule