readme.txt

来自「Altera 官方提供的SDRAM控制器,verilog的」· 文本 代码 · 共 27 行

SDR SDRAM Controller Verilog Reference Design version 1.1.


This readme files describes the contents of each directory of the SDR SDRAM Controller reference design version 1.1 and 
the new feature in the current version.

File/Directory				Description
=============================================================================
\doc				SDR SDRAM reference design documentation
\model				Contains the verilog SDRAM model
\route				Contains the Quartus 2000.05 project files for the controller design.
\simulation			Contains the verilog testbench, modelsim project file, and library
\source				Contains the verilog source files for the SDR SDRAM reference design
\synthesis\synplicity		Contains all synplicity project files associated with synthesizing the reference design 




New Feature in SDR SDRAM Controller Verilog Reference Design version 1.1
=============================================================================

The SDR SDRAM Controller Reference Design version 1.1 issues a Burst terminate command to the SDRAM device when the device is
in Page Mode operation.  In a Page Mode operation, in order to terminate the burst transfer, the user needs to issue a 
precharge command as described in the \doc\SDR_SDRAM.pdf.  The controller will then issue a Burst Terminate command to 
the SDRAM device. In the previous version, the SDR SDRAM controller will issue a precharge to the SDRAM device in order to stop the burst.