sdr_sdram.esf

来自「Altera 官方提供的SDRAM控制器,verilog的」· ESF 代码 · 共 18 行

OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
	|BA : FAST_OUTPUT_REGISTER = ON;
	|CAS_N : FAST_OUTPUT_REGISTER = ON;
	|CKE : FAST_OUTPUT_REGISTER = ON;
	|CS_N : FAST_OUTPUT_REGISTER = ON;
	|DATAOUT : FAST_OUTPUT_REGISTER = ON;
	|RAS_N : FAST_OUTPUT_REGISTER = ON;
	|SA : FAST_OUTPUT_REGISTER = ON;
	|WE_N : FAST_OUTPUT_REGISTER = ON;
	|ADDR : FAST_INPUT_REGISTER = ON;
	|DQ : FAST_INPUT_REGISTER = ON;
}
TIMING_REQUIREMENTS
{
	"|command:command1|OE" : CUT = ON;
}