ebiu.vhd

It contains a vhdl description of the external bus interface unit for 68000 processor. currently onl

Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Unsigned.All;

Library Work;
Use Work.defines.All;

Entity ebiu Is
  Port(
  			sysclk					: In Std_Logic;
  			cpuclk					: In Std_Logic;
  			reset						: In Std_Logic;
  			
  			din							: In Std_Logic_Vector(31 Downto 0);
  			dout						: Out Std_Logic_Vector(31 Downto 0);
  			wradd						: In Regadd_Types;
  			wrpls						: In Std_Logic;
  			
  			
  			cycreq					: In Std_Logic;
  			cyctype					: In Cycle_Types;
  			cycsize					: In Size_Types;
  			cyccmp					: Out Std_Logic;
  			
  			add							: Out Std_Logic_Vector(23 Downto 1);
  			datain					: In Std_Logic_Vector(15 Downto 0);
  			dataout					: Out Std_Logic_Vector(15 Downto 0);
  			fc							: Out Std_Logic_Vector(2 Downto 0);
  			as_l						: Out Std_Logic;
  			uds_l						: Out Std_Logic;
  			lds_l						: Out Std_Logic;
  			rw_l						: Out Std_Logic;
  			dtack_l					: In Std_Logic;
  			
  			ebiu_stm_probe	: Out Ebiu_States
  		);
End ebiu;

Architecture ebiu_a Of ebiu Is

	Signal ebiu_stm				: Ebiu_States;
	Signal posedge				: Std_logic;
	Signal negedge				: Std_Logic;	
	Signal d_cpuclk				: Std_Logic;
	Signal hilo						: Std_Logic;
	Signal marreg					: Std_Logic_Vector(31 Downto 0);
	Signal mdrreg					: Std_Logic_Vector(31 Downto 0);
	Signal mdwreg					: STd_Logic_Vector(31 Downto 0);
	
Begin

Process(sysclk,reset)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  		d_cpuclk <= cpuclk;
  End If;
End Process;

posedge <= cpuclk And Not d_cpuclk;
negedge <= Not cpuclk And d_cpuclk;

Process(sysclk,reset,wradd,wrpls,din)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  	If (reset = '1') Then
  		marreg <= (Others => '0');
  	Elsif (wradd = ADDMAR And wrpls = '1') Then
  		marreg <= din;
  	End If;
  End If;
End Process;

Process(sysclk,reset,wradd,wrpls,din)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  	If (reset = '1') Then
  		mdwreg <= (Others => '0');
  	Elsif (wradd = ADDMDR And wrpls = '1') Then
  		mdwreg <= din;
  	End If;
  End If;
End Process;

Process(sysclk,reset,datain,hilo,cycsize,cyctype,ebiu_stm)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  	If (reset = '1') Then
  		mdrreg <= (Others => '0');
  	Elsif (cyctype = CYCRD Or cyctype = CYCRMW) Then
  		If (ebiu_stm = S5) Then 
  			If (cycsize /= BYTE) Then
  					mdrreg(15 Downto 0) <= datain;
  			Else
  				If (hilo = '0') Then
  					mdrreg(31 Downto 16) <= datain;
  				Else
  					mdrreg(15 Downto 0) <= datain;
  				End If;
  			End If;
  		End If;
  	End If;
  End If;
End Process;


Process(sysclk,reset,ebiu_stm)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  	If (reset = '1') Then
  		ebiu_stm <= EBIDLE;
  	Else
  		Case ebiu_stm Is
  			When EBIDLE =>
  				If (negedge = '1') Then
  					If (cycreq = '1') Then
  						ebiu_stm <= S0;
  					End If;
  				End If;
  			When S0			=>
  				If (posedge = '1') Then
  					ebiu_stm <= S1;
  				End If;
  			When S1			=>
  					If (negedge = '1') Then
  						ebiu_stm <= S2;
  					End If;
   			When S2			=>
  				If (posedge = '1') Then
  					ebiu_stm <= S3;
  				End If;
  			When S3			=>
  					If (negedge = '1') Then
  						ebiu_stm <= S4;
  					End If;
  			When S4			=>
  				If (posedge = '1') Then
  					If (dtack_l = '0') Then
  						ebiu_stm <= S5;
  					End If;
  				End If;
  			When S5			=>
  					If (negedge = '1') Then
  						ebiu_stm <= S6;
  					End If;
  			When S6			=>
  				If (posedge = '1') Then
  					ebiu_stm <= S7;
  				End If;
  			When S7			=>
					If (negedge = '1') Then
						If (cyctype = CYCRMW) Then
							ebiu_stm <= S8;
						Elsif (hilo = '0' And cycsize = LONG) Then
							ebiu_stm <= S0;
						Else
							ebiu_stm <= EBIDLE;
						End If;
					End If;
				When S8 =>
					If (posedge = '1') Then
						ebiu_stm <= S9;
					End If;
				When S9 =>
					If (negedge = '1') Then
						ebiu_stm <= S10;
					End If;
				When S10 =>
					If (posedge = '1') Then
						ebiu_stm <= S11;
					End If;
				When S11 =>
					If (negedge = '1') Then
						ebiu_stm <= S12;
					End If;
				When S12 =>
					If (posedge = '1') Then
						ebiu_stm <= S13;
					End If;
				When S13 =>
					If (negedge = '1') Then
						ebiu_stm <= S14;
					End If;
				When S14 =>
					If (posedge = '1') Then
						ebiu_stm <= S15;
					End If;
				When S15 =>
					If (negedge = '1') Then
						ebiu_stm <= S16;
					End If;
				When S16 =>
					If (posedge = '1') Then
					  If (dtack_l = '0') Then
							ebiu_stm <= S17;
						End If;
					End If;
				When S17 =>
					If (negedge = '1') Then
						ebiu_stm <= S18;
					End If;
				When S18 =>
					If (posedge = '1') Then
						ebiu_stm <= S19;
					End If;
				When S19 =>  					
					If (negedge = '1') Then
						ebiu_stm <= EBIDLE;
					End If;
  		End Case;
  	End If;
  End If;
End Process;

Process(sysclk,reset,ebiu_stm)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  	If (reset = '1') Then
  		hilo <= '0';
  	Elsif (ebiu_stm = EBIDLE) Then
  		hilo <= '0';
  	Elsif (ebiu_stm = S7 And cycsize = LONG And cyctype /= CYCRMW) Then
  		hilo <= '1';
  	End If;
  End If;
End Process;

ebiu_stm_probe <= ebiu_stm;

cyccmp <= '1' When (ebiu_stm = S7 And cycsize /= LONG) Else
					'1' When (ebiu_stm = S7 And cycsize = LONG And hilo = '1') Else 
					'1' When (ebiu_stm = S19) Else '0';

as_l <= '1' When ((ebiu_stm = EBIDLE) Or (ebiu_stm =  S0) Or (ebiu_stm = S1) Or (ebiu_stm = S7 And cyctype /= CYCRMW) Or (ebiu_stm = S19)) Else '0';
lds_l <= marreg(0) When (cycsize = BYTE) Else '0';
uds_l <= Not marreg(0) When (cycsize = BYTE) Else '0';
fc <= "000";
rw_l <= '1' When (cyctype = CYCRD) Else
		    '0' When (cyctype = CYCWR) Else
		    '0' When ((ebiu_stm = S8)  Or (ebiu_stm = S9) Or (ebiu_stm = S10) Or (ebiu_stm = S11) Or (ebiu_stm = S12) Or 
		    				 (ebiu_stm = S13) Or (ebiu_stm = S14) Or (ebiu_stm = S15) Or (ebiu_stm = S16) Or (ebiu_stm = S17) Or
		    				 (ebiu_stm = S18)) Else '1';  
add <= marreg(23 Downto 1) When (hilo = '0') Else (marreg(23 Downto 1) + 2);

dataout <= mdwreg(31 Downto 16) When (cycsize = LONG) Else mdwreg(15 Downto 0);
dout <= mdrreg;  
End ebiu_a;