defines.vhd

来自「It contains a vhdl description of the ex」· VHDL 代码 · 共 13 行

Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Unsigned.All;

Package defines Is
	Type size_types Is(BYTE,WORD,LONG);
	Type cycle_types Is(CYCRD,CYCWR,CYCRMW);
	Type regadd_types IS (ADDMAR,ADDMDR);
	Type ebiu_states Is(EBIDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19);
End Package defines;

Package Body defines Is
End Package Body defines;