tb_ebiu.vhd

It contains a vhdl description of the external bus interface unit for 68000 processor. currently onl

Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Unsigned.All;

Library Work;
Use Work.defines.All;

Entity tb_ebiu Is
End tb_ebiu;

Architecture tb_ebiu_a Of tb_ebiu Is

Component ebiu 
  Port(
  			sysclk					: In Std_Logic;
  			cpuclk					: In Std_Logic;
  			reset						: In Std_Logic;
  			
  			din							: In Std_Logic_Vector(31 Downto 0);
  			dout						: Out Std_Logic_Vector(31 Downto 0);
  			wradd						: In Regadd_Types;
  			wrpls						: In Std_Logic;  			
  			
  			cycreq					: In Std_Logic;
  			cyctype					: In Cycle_Types;
  			cycsize					: In Size_Types;
  			cyccmp					: Out Std_Logic;

  			add							: Out Std_Logic_Vector(23 Downto 1);
  			datain					: In Std_Logic_Vector(15 Downto 0);
  			dataout					: Out Std_Logic_Vector(15 Downto 0);
  			fc							: Out Std_Logic_Vector(2 Downto 0);
  			as_l						: Out Std_Logic;
  			uds_l						: Out Std_Logic;
  			lds_l						: Out Std_Logic;
  			rw_l						: Out Std_Logic;
  			dtack_l					: In Std_Logic;
  			
  			ebiu_stm_probe	: Out Ebiu_States
  		);
End Component;

Signal sysclk				: Std_Logic := '0';
Signal cpuclk				: Std_Logic := '0';
Signal reset				: Std_Logic := '1';
Signal din					: Std_Logic_Vector(31 Downto 0);
Signal dout					: Std_Logic_Vector(31 Downto 0);
Signal wradd				: RegAdd_Types;
Signal wrpls				: Std_Logic := '0';
Signal cycreq				: Std_logic;
Signal cyctype			: Cycle_Types;
Signal cycsize			: Size_Types;
Signal cyccmp				: Std_Logic;
Signal add					: Std_Logic_Vector(23 Downto 1);
Signal datain				: Std_Logic_Vector(15 Downto 0);
Signal dataout			: Std_Logic_Vector(15 Downto 0);
Signal fc						: Std_Logic_Vector(2 Downto 0);
Signal as_l					: Std_Logic;
Signal uds_l				: Std_Logic;
Signal lds_l				: Std_Logic;
SIgnal rw_l					: Std_Logic;
Signal dtack_l			: Std_Logic := '1';
Signal ebiu_stm_probe	: Ebiu_States;

Type tb_ebiu_states Is(TIDLE,TB0,TB1,TB2,TB3,TB4);
Signal tb_ebiu_stm	: Tb_Ebiu_States;

Signal tbcounter		: Std_Logic_Vector(5 Downto 0);

Begin

UUT : ebiu Port Map(
											sysclk,cpuclk,reset,din,dout,wradd,wrpls,cycreq,cyctype,cycsize,cyccmp,add,datain,dataout,fc,as_l,uds_l,lds_l,rw_l,dtack_l,ebiu_stm_probe
									 );
									 
sysclk <= Not sysclk After 100 ns;
Process(sysclk,reset)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  		cpuclk <= Not cpuclk;
  End If;
End Process;			

reset <= '0' After 400 ns;

		 
Process(cpuclk,reset,dtack_l,ebiu_stm_probe)
Begin
  If (cpuclk = '1' And cpuclk'Event) Then
  	If (reset = '1') Then
  		dtack_l <= '1';
  	Else
  		If (ebiu_stm_probe = S4) Then
  			dtack_l <= '0';
  		Elsif (ebiu_stm_probe = S7) Then
  			dtack_l <= '1';
  		Elsif (ebiu_stm_probe = S16) Then
  			dtack_l <= '0';
  		Elsif (ebiu_stm_probe = S19) Then
  			dtack_l <= '1';
  		End If;
  	End If;
  End If;
End Process;

Process(sysclk,reset,tb_ebiu_stm)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  	If (reset = '1') Then
  		tbcounter <= (Others => '0');
  	Elsif (tb_ebiu_stm = TB4) Then
  		tbcounter <= tbcounter + 1;
  	End If;
  End If;
End Process;

Process(sysclk,reset,tb_ebiu_stm)
Begin
  If (sysclk = '1' And sysclk'Event) Then
  	If (reset = '1') Then
  		tb_ebiu_stm <= TIDLE;
  	Else
  		Case tb_ebiu_stm Is
  			When TIDLE 	=>
  				tb_ebiu_stm <= TB0;
  			When TB0		=>
  				tb_ebiu_stm <= TB1;
  			When TB1		=>
  				If (as_l = '0') Then
  					tb_ebiu_stm <= TB2;
  				End If;
  			When TB2		=>
  				If (cyccmp = '1') Then
  					tb_ebiu_stm <= TB3;
  				End If;
  			When TB3		=>
  				tb_ebiu_stm <= TB4;
  			When TB4		=>
  				tb_ebiu_stm <= TIDLE;  				
  		End Case;
  	End If;
  End If;
End Process;

cycreq <= '1' When ((tb_ebiu_stm = TB0) Or (tb_ebiu_stm = TB1) Or (tb_ebiu_stm = TB2)) Else '0'; 
			 
Process(tbcounter)
Begin
  Case tbcounter Is
  	When "000000" =>
  		din <= x"AAAA0000";
  		datain <= x"1234";
  		cyctype <= CYCRD;
  		cycsize	<= BYTE;
		When "000001" =>
  		din <= x"AAAA0000";
  		datain <= x"1234";
  		cyctype <= CYCRD;
  		cycsize	<= WORD;
		When "000010" =>
  		din <= x"AAAA0000";
  		datain <= x"1234";
  		cyctype <= CYCRD;
  		cycsize	<= LONG;
		When Others =>
  		din <= x"AAAA0000";
  		datain <= x"1234";
			cyctype <= CYCRD;
			cycsize <= BYTE;
  End Case;
End Process;			 
End tb_ebiu_a;