parity_verifier.tan.qmsg

学习UART知识

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 09 21:39:22 2007 " "Info: Processing started: Sat Jun 09 21:39:22 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off parity_verifier -c parity_verifier --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off parity_verifier -c parity_verifier --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "source\[0\] parity 11.316 ns Longest " "Info: Longest tpd from source pin \"source\[0\]\" to destination pin \"parity\" is 11.316 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns source\[0\] 1 PIN PIN_133 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_133; Fanout = 1; PIN Node = 'source\[0\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" Compiler "parity_verifier" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/" "" "" { source[0] } "NODE_NAME" } "" } } { "parity_verifier.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/parity_verifier.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.335 ns) + CELL(0.590 ns) 7.400 ns check~46 2 COMB LC_X12_Y13_N5 1 " "Info: 2: + IC(5.335 ns) + CELL(0.590 ns) = 7.400 ns; Loc. = LC_X12_Y13_N5; Fanout = 1; COMB Node = 'check~46'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" Compiler "parity_verifier" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/" "" "5.925 ns" { source[0] check~46 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.114 ns) 7.930 ns check~6 3 COMB LC_X12_Y13_N4 1 " "Info: 3: + IC(0.416 ns) + CELL(0.114 ns) = 7.930 ns; Loc. = LC_X12_Y13_N4; Fanout = 1; COMB Node = 'check~6'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" Compiler "parity_verifier" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/" "" "0.530 ns" { check~46 check~6 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.278 ns) + CELL(2.108 ns) 11.316 ns parity 4 PIN PIN_129 0 " "Info: 4: + IC(1.278 ns) + CELL(2.108 ns) = 11.316 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'parity'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" Compiler "parity_verifier" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/" "" "3.386 ns" { check~6 parity } "NODE_NAME" } "" } } { "parity_verifier.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/parity_verifier.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.287 ns 37.88 % " "Info: Total cell delay = 4.287 ns ( 37.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.029 ns 62.12 % " "Info: Total interconnect delay = 7.029 ns ( 62.12 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier_cmp.qrpt" Compiler "parity_verifier" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/db/parity_verifier.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/" "" "11.316 ns" { source[0] check~46 check~6 parity } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.316 ns" { source[0] source[0]~out0 check~46 check~6 parity } { 0.000ns 0.000ns 5.335ns 0.416ns 1.278ns } { 0.000ns 1.475ns 0.590ns 0.114ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 09 21:39:22 2007 " "Info: Processing ended: Sat Jun 09 21:39:22 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}