transmitter.tan.qmsg

学习UART知识

{ "Info" "ITDB_TSU_RESULT" "txd_shift\[1\] tbuf\[1\] baud_clk 6.197 ns register " "Info: tsu for register \"txd_shift\[1\]\" (data pin = \"tbuf\[1\]\", clock pin = \"baud_clk\") is 6.197 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.890 ns + Longest pin register " "Info: + Longest pin to register delay is 8.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns tbuf\[1\] 1 PIN PIN_122 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 1; PIN Node = 'tbuf\[1\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { tbuf[1] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.677 ns) + CELL(0.738 ns) 8.890 ns txd_shift\[1\] 2 REG LC_X9_Y3_N0 1 " "Info: 2: + IC(6.677 ns) + CELL(0.738 ns) = 8.890 ns; Loc. = LC_X9_Y3_N0; Fanout = 1; REG Node = 'txd_shift\[1\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "7.415 ns" { tbuf[1] txd_shift[1] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.213 ns ( 24.89 % ) " "Info: Total cell delay = 2.213 ns ( 24.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.677 ns ( 75.11 % ) " "Info: Total interconnect delay = 6.677 ns ( 75.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "8.890 ns" { tbuf[1] txd_shift[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "8.890 ns" { tbuf[1] tbuf[1]~out0 txd_shift[1] } { 0.000ns 0.000ns 6.677ns } { 0.000ns 1.475ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns - Shortest register " "Info: - Shortest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'baud_clk'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud_clk } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns txd_shift\[1\] 2 REG LC_X9_Y3_N0 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y3_N0; Fanout = 1; REG Node = 'txd_shift\[1\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { baud_clk txd_shift[1] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd_shift[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd_shift[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "8.890 ns" { tbuf[1] txd_shift[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "8.890 ns" { tbuf[1] tbuf[1]~out0 txd_shift[1] } { 0.000ns 0.000ns 6.677ns } { 0.000ns 1.475ns 0.738ns } "" } } { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd_shift[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd_shift[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "baud_clk txd txd~reg0 8.020 ns register " "Info: tco from clock \"baud_clk\" to destination pin \"txd\" through register \"txd~reg0\" is 8.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"baud_clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'baud_clk'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud_clk } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns txd~reg0 2 REG LC_X9_Y4_N5 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y4_N5; Fanout = 1; REG Node = 'txd~reg0'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { baud_clk txd~reg0 } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd~reg0 } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.066 ns + Longest register pin " "Info: + Longest register to pin delay is 5.066 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txd~reg0 1 REG LC_X9_Y4_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y4_N5; Fanout = 1; REG Node = 'txd~reg0'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { txd~reg0 } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.942 ns) + CELL(2.124 ns) 5.066 ns txd 2 PIN PIN_7 0 " "Info: 2: + IC(2.942 ns) + CELL(2.124 ns) = 5.066 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'txd'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "5.066 ns" { txd~reg0 txd } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 41.93 % ) " "Info: Total cell delay = 2.124 ns ( 41.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.942 ns ( 58.07 % ) " "Info: Total interconnect delay = 2.942 ns ( 58.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "5.066 ns" { txd~reg0 txd } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "5.066 ns" { txd~reg0 txd } { 0.000ns 2.942ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd~reg0 } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "5.066 ns" { txd~reg0 txd } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "5.066 ns" { txd~reg0 txd } { 0.000ns 2.942ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "txd_shift\[6\] tbuf\[6\] baud_clk -4.327 ns register " "Info: th for register \"txd_shift\[6\]\" (data pin = \"tbuf\[6\]\", clock pin = \"baud_clk\") is -4.327 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'baud_clk'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud_clk } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns txd_shift\[6\] 2 REG LC_X9_Y3_N8 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y3_N8; Fanout = 1; REG Node = 'txd_shift\[6\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { baud_clk txd_shift[6] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd_shift[6] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd_shift[6] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.072 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns tbuf\[6\] 1 PIN PIN_47 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 1; PIN Node = 'tbuf\[6\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { tbuf[6] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.990 ns) + CELL(0.607 ns) 7.072 ns txd_shift\[6\] 2 REG LC_X9_Y3_N8 1 " "Info: 2: + IC(4.990 ns) + CELL(0.607 ns) = 7.072 ns; Loc. = LC_X9_Y3_N8; Fanout = 1; REG Node = 'txd_shift\[6\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "5.597 ns" { tbuf[6] txd_shift[6] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 29.44 % ) " "Info: Total cell delay = 2.082 ns ( 29.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.990 ns ( 70.56 % ) " "Info: Total interconnect delay = 4.990 ns ( 70.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "7.072 ns" { tbuf[6] txd_shift[6] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "7.072 ns" { tbuf[6] tbuf[6]~out0 txd_shift[6] } { 0.000ns 0.000ns 4.990ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd_shift[6] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd_shift[6] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "7.072 ns" { tbuf[6] txd_shift[6] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "7.072 ns" { tbuf[6] tbuf[6]~out0 txd_shift[6] } { 0.000ns 0.000ns 4.990ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 12 17:03:53 2008 " "Info: Processing ended: Sat Apr 12 17:03:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}