transmitter.tan.qmsg

学习UART知识

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 12 17:03:52 2008 " "Info: Processing started: Sat Apr 12 17:03:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off transmitter -c transmitter --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off transmitter -c transmitter --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "baud_clk " "Info: Assuming node \"baud_clk\" is an undefined clock" {  } { { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 7 -1 0 } } { "d:/altera/quartus61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus61/quartus/bin/Assignment Editor.qase" 1 { { 0 "baud_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "baud_clk register txcnt16\[0\] register txd_cnt\[1\] 256.34 MHz 3.901 ns Internal " "Info: Clock \"baud_clk\" has Internal fmax of 256.34 MHz between source register \"txcnt16\[0\]\" and destination register \"txd_cnt\[1\]\" (period= 3.901 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.640 ns + Longest register register " "Info: + Longest register to register delay is 3.640 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txcnt16\[0\] 1 REG LC_X10_Y3_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y3_N1; Fanout = 5; REG Node = 'txcnt16\[0\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { txcnt16[0] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.748 ns) + CELL(0.590 ns) 1.338 ns Equal0~21 2 COMB LC_X9_Y3_N9 6 " "Info: 2: + IC(0.748 ns) + CELL(0.590 ns) = 1.338 ns; Loc. = LC_X9_Y3_N9; Fanout = 6; COMB Node = 'Equal0~21'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "1.338 ns" { txcnt16[0] Equal0~21 } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.292 ns) 2.897 ns txd_cnt\[2\]~746 3 COMB LC_X10_Y4_N6 3 " "Info: 3: + IC(1.267 ns) + CELL(0.292 ns) = 2.897 ns; Loc. = LC_X10_Y4_N6; Fanout = 3; COMB Node = 'txd_cnt\[2\]~746'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { Equal0~21 txd_cnt[2]~746 } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.309 ns) 3.640 ns txd_cnt\[1\] 4 REG LC_X10_Y4_N0 7 " "Info: 4: + IC(0.434 ns) + CELL(0.309 ns) = 3.640 ns; Loc. = LC_X10_Y4_N0; Fanout = 7; REG Node = 'txd_cnt\[1\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "0.743 ns" { txd_cnt[2]~746 txd_cnt[1] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.191 ns ( 32.72 % ) " "Info: Total cell delay = 1.191 ns ( 32.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.449 ns ( 67.28 % ) " "Info: Total interconnect delay = 2.449 ns ( 67.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "3.640 ns" { txcnt16[0] Equal0~21 txd_cnt[2]~746 txd_cnt[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "3.640 ns" { txcnt16[0] Equal0~21 txd_cnt[2]~746 txd_cnt[1] } { 0.000ns 0.748ns 1.267ns 0.434ns } { 0.000ns 0.590ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'baud_clk'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud_clk } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns txd_cnt\[1\] 2 REG LC_X10_Y4_N0 7 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X10_Y4_N0; Fanout = 7; REG Node = 'txd_cnt\[1\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { baud_clk txd_cnt[1] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd_cnt[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd_cnt[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"baud_clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'baud_clk'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud_clk } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns txcnt16\[0\] 2 REG LC_X10_Y3_N1 5 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X10_Y3_N1; Fanout = 5; REG Node = 'txcnt16\[0\]'" {  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "1.261 ns" { baud_clk txcnt16[0] } "NODE_NAME" } } { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txcnt16[0] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txcnt16[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd_cnt[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd_cnt[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txcnt16[0] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txcnt16[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "transmitter.vhd" "" { Text "J:/uart/VHDLoo/transmitter/transmitter.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "3.640 ns" { txcnt16[0] Equal0~21 txd_cnt[2]~746 txd_cnt[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "3.640 ns" { txcnt16[0] Equal0~21 txd_cnt[2]~746 txd_cnt[1] } { 0.000ns 0.748ns 1.267ns 0.434ns } { 0.000ns 0.590ns 0.292ns 0.309ns } "" } } { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txd_cnt[1] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txd_cnt[1] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus61/quartus/bin/TimingClosureFloorplan.fld" "" "2.730 ns" { baud_clk txcnt16[0] } "NODE_NAME" } } { "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus61/quartus/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 txcnt16[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}