baud_rate.map.qmsg

学习UART知识

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 16 22:33:59 2008 " "Info: Processing started: Sun Mar 16 22:33:59 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off baud_rate -c baud_rate " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off baud_rate -c baud_rate" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baud_rate.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file baud_rate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 baud_rate-baud_rate " "Info: Found design unit 1: baud_rate-baud_rate" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 baud_rate " "Info: Found entity 1: baud_rate" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "baud_rate " "Info: Elaborating entity \"baud_rate\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "baud_clk baud_rate.vhd(41) " "Warning (10492): VHDL Process Statement warning at baud_rate.vhd(41): signal \"baud_clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 41 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fre_div_factor\[9\] data_in GND " "Warning: Reduced register \"fre_div_factor\[9\]\" with stuck data_in port to stuck value GND" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fre_div_factor\[12\] data_in GND " "Warning: Reduced register \"fre_div_factor\[12\]\" with stuck data_in port to stuck value GND" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fre_div_factor\[8\] fre_div_factor\[2\] " "Info: Duplicate register \"fre_div_factor\[8\]\" merged to single register \"fre_div_factor\[2\]\"" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "fre_div_factor\[7\] fre_div_factor\[5\] " "Info: Duplicate register \"fre_div_factor\[7\]\" merged to single register \"fre_div_factor\[5\]\"" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "fre_div_factor\[11\] fre_div_factor\[5\] " "Info: Duplicate register \"fre_div_factor\[11\]\" merged to single register \"fre_div_factor\[5\]\"" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "fre_div_factor\[13\] fre_div_factor\[5\] " "Info: Duplicate register \"fre_div_factor\[13\]\" merged to single register \"fre_div_factor\[5\]\"" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "92 " "Info: Implemented 92 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "87 " "Info: Implemented 87 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 16 22:34:03 2008 " "Info: Processing ended: Sun Mar 16 22:34:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}