📄 baud_rate.tan.qmsg

📁 学习UART知识
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register fre_div_factor\[3\] register baud_clk 93.08 MHz 10.744 ns Internal " "Info: Clock \"clk\" has Internal fmax of 93.08 MHz between source register \"fre_div_factor\[3\]\" and destination register \"baud_clk\" (period= 10.744 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.483 ns + Longest register register " "Info: + Longest register to register delay is 10.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fre_div_factor\[3\] 1 REG LC_X23_Y11_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y11_N2; Fanout = 4; REG Node = 'fre_div_factor\[3\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fre_div_factor[3] } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.456 ns) + CELL(0.432 ns) 1.888 ns Add0~240COUT1 2 COMB LC_X18_Y11_N6 2 " "Info: 2: + IC(1.456 ns) + CELL(0.432 ns) = 1.888 ns; Loc. = LC_X18_Y11_N6; Fanout = 2; COMB Node = 'Add0~240COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.888 ns" { fre_div_factor[3] Add0~240COUT1 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.968 ns Add0~258COUT1 3 COMB LC_X18_Y11_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.968 ns; Loc. = LC_X18_Y11_N7; Fanout = 2; COMB Node = 'Add0~258COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add0~240COUT1 Add0~258COUT1 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.048 ns Add0~246COUT1 4 COMB LC_X18_Y11_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.048 ns; Loc. = LC_X18_Y11_N8; Fanout = 2; COMB Node = 'Add0~246COUT1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add0~258COUT1 Add0~246COUT1 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.306 ns Add0~264 5 COMB LC_X18_Y11_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 2.306 ns; Loc. = LC_X18_Y11_N9; Fanout = 6; COMB Node = 'Add0~264'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { Add0~246COUT1 Add0~264 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.985 ns Add0~251 6 COMB LC_X18_Y10_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.985 ns; Loc. = LC_X18_Y10_N4; Fanout = 1; COMB Node = 'Add0~251'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { Add0~264 Add0~251 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.292 ns) 3.714 ns Equal0~166 7 COMB LC_X18_Y10_N9 1 " "Info: 7: + IC(0.437 ns) + CELL(0.292 ns) = 3.714 ns; Loc. = LC_X18_Y10_N9; Fanout = 1; COMB Node = 'Equal0~166'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.729 ns" { Add0~251 Equal0~166 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.590 ns) 5.546 ns Equal0~167 8 COMB LC_X19_Y11_N6 28 " "Info: 8: + IC(1.242 ns) + CELL(0.590 ns) = 5.546 ns; Loc. = LC_X19_Y11_N6; Fanout = 28; COMB Node = 'Equal0~167'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.832 ns" { Equal0~166 Equal0~167 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.590 ns) 6.919 ns Add1~463 9 COMB LC_X20_Y11_N8 2 " "Info: 9: + IC(0.783 ns) + CELL(0.590 ns) = 6.919 ns; Loc. = LC_X20_Y11_N8; Fanout = 2; COMB Node = 'Add1~463'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { Equal0~167 Add1~463 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.590 ns) 9.014 ns Equal1~114 10 COMB LC_X19_Y12_N3 1 " "Info: 10: + IC(1.505 ns) + CELL(0.590 ns) = 9.014 ns; Loc. = LC_X19_Y12_N3; Fanout = 1; COMB Node = 'Equal1~114'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.095 ns" { Add1~463 Equal1~114 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.114 ns) 9.555 ns Equal1~117 11 COMB LC_X19_Y12_N9 1 " "Info: 11: + IC(0.427 ns) + CELL(0.114 ns) = 9.555 ns; Loc. = LC_X19_Y12_N9; Fanout = 1; COMB Node = 'Equal1~117'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.541 ns" { Equal1~114 Equal1~117 } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.478 ns) 10.483 ns baud_clk 12 REG LC_X19_Y12_N2 2 " "Info: 12: + IC(0.450 ns) + CELL(0.478 ns) = 10.483 ns; Loc. = LC_X19_Y12_N2; Fanout = 2; REG Node = 'baud_clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.928 ns" { Equal1~117 baud_clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.183 ns ( 39.90 % ) " "Info: Total cell delay = 4.183 ns ( 39.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns ( 60.10 % ) " "Info: Total interconnect delay = 6.300 ns ( 60.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "10.483 ns" { fre_div_factor[3] Add0~240COUT1 Add0~258COUT1 Add0~246COUT1 Add0~264 Add0~251 Equal0~166 Equal0~167 Add1~463 Equal1~114 Equal1~117 baud_clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "10.483 ns" { fre_div_factor[3] Add0~240COUT1 Add0~258COUT1 Add0~246COUT1 Add0~264 Add0~251 Equal0~166 Equal0~167 Add1~463 Equal1~114 Equal1~117 baud_clk } { 0.000ns 1.456ns 0.000ns 0.000ns 0.000ns 0.000ns 0.437ns 1.242ns 0.783ns 1.505ns 0.427ns 0.450ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.292ns 0.590ns 0.590ns 0.590ns 0.114ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns baud_clk 2 REG LC_X19_Y12_N2 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X19_Y12_N2; Fanout = 2; REG Node = 'baud_clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk baud_clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk baud_clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 baud_clk } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns fre_div_factor\[3\] 2 REG LC_X23_Y11_N2 4 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X23_Y11_N2; Fanout = 4; REG Node = 'fre_div_factor\[3\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk fre_div_factor[3] } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk fre_div_factor[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 fre_div_factor[3] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk baud_clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 baud_clk } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk fre_div_factor[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 fre_div_factor[3] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "10.483 ns" { fre_div_factor[3] Add0~240COUT1 Add0~258COUT1 Add0~246COUT1 Add0~264 Add0~251 Equal0~166 Equal0~167 Add1~463 Equal1~114 Equal1~117 baud_clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "10.483 ns" { fre_div_factor[3] Add0~240COUT1 Add0~258COUT1 Add0~246COUT1 Add0~264 Add0~251 Equal0~166 Equal0~167 Add1~463 Equal1~114 Equal1~117 baud_clk } { 0.000ns 1.456ns 0.000ns 0.000ns 0.000ns 0.000ns 0.437ns 1.242ns 0.783ns 1.505ns 0.427ns 0.450ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.292ns 0.590ns 0.590ns 0.590ns 0.114ns 0.478ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk baud_clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 baud_clk } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk fre_div_factor[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 fre_div_factor[3] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "fre_div_factor\[2\] baud_sel\[0\] clk 5.247 ns register " "Info: tsu for register \"fre_div_factor\[2\]\" (data pin = \"baud_sel\[0\]\", clock pin = \"clk\") is 5.247 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.992 ns + Longest pin register " "Info: + Longest pin to register delay is 7.992 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns baud_sel\[0\] 1 PIN PIN_111 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_111; Fanout = 7; PIN Node = 'baud_sel\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud_sel[0] } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.779 ns) + CELL(0.738 ns) 7.992 ns fre_div_factor\[2\] 2 REG LC_X18_Y11_N1 8 " "Info: 2: + IC(5.779 ns) + CELL(0.738 ns) = 7.992 ns; Loc. = LC_X18_Y11_N1; Fanout = 8; REG Node = 'fre_div_factor\[2\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.517 ns" { baud_sel[0] fre_div_factor[2] } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.213 ns ( 27.69 % ) " "Info: Total cell delay = 2.213 ns ( 27.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.779 ns ( 72.31 % ) " "Info: Total interconnect delay = 5.779 ns ( 72.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.992 ns" { baud_sel[0] fre_div_factor[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.992 ns" { baud_sel[0] baud_sel[0]~out0 fre_div_factor[2] } { 0.000ns 0.000ns 5.779ns } { 0.000ns 1.475ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns fre_div_factor\[2\] 2 REG LC_X18_Y11_N1 8 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X18_Y11_N1; Fanout = 8; REG Node = 'fre_div_factor\[2\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk fre_div_factor[2] } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk fre_div_factor[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 fre_div_factor[2] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.992 ns" { baud_sel[0] fre_div_factor[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.992 ns" { baud_sel[0] baud_sel[0]~out0 fre_div_factor[2] } { 0.000ns 0.000ns 5.779ns } { 0.000ns 1.475ns 0.738ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk fre_div_factor[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 fre_div_factor[2] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk bclk baud_clk 7.992 ns register " "Info: tco from clock \"clk\" to destination pin \"bclk\" through register \"baud_clk\" is 7.992 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns baud_clk 2 REG LC_X19_Y12_N2 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X19_Y12_N2; Fanout = 2; REG Node = 'baud_clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk baud_clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk baud_clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 baud_clk } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.986 ns + Longest register pin " "Info: + Longest register to pin delay is 4.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns baud_clk 1 REG LC_X19_Y12_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y12_N2; Fanout = 2; REG Node = 'baud_clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { baud_clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.862 ns) + CELL(2.124 ns) 4.986 ns bclk 2 PIN PIN_3 0 " "Info: 2: + IC(2.862 ns) + CELL(2.124 ns) = 4.986 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'bclk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { baud_clk bclk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 42.60 % ) " "Info: Total cell delay = 2.124 ns ( 42.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.862 ns ( 57.40 % ) " "Info: Total interconnect delay = 2.862 ns ( 57.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { baud_clk bclk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { baud_clk bclk } { 0.000ns 2.862ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk baud_clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 baud_clk } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.986 ns" { baud_clk bclk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.986 ns" { baud_clk bclk } { 0.000ns 2.862ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "fre_div_factor\[5\] rst clk -0.717 ns register " "Info: th for register \"fre_div_factor\[5\]\" (data pin = \"rst\", clock pin = \"clk\") is -0.717 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 23; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns fre_div_factor\[5\] 2 REG LC_X19_Y10_N9 14 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X19_Y10_N9; Fanout = 14; REG Node = 'fre_div_factor\[5\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk fre_div_factor[5] } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk fre_div_factor[5] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 fre_div_factor[5] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.514 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.514 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_16 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 23; PIN Node = 'rst'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.867 ns) 3.514 ns fre_div_factor\[5\] 2 REG LC_X19_Y10_N9 14 " "Info: 2: + IC(1.178 ns) + CELL(0.867 ns) = 3.514 ns; Loc. = LC_X19_Y10_N9; Fanout = 14; REG Node = 'fre_div_factor\[5\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.045 ns" { rst fre_div_factor[5] } "NODE_NAME" } } { "baud_rate.vhd" "" { Text "L:/uart/VHDLoo/baud_rate/baud_rate.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 66.48 % ) " "Info: Total cell delay = 2.336 ns ( 66.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.178 ns ( 33.52 % ) " "Info: Total interconnect delay = 1.178 ns ( 33.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.514 ns" { rst fre_div_factor[5] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.514 ns" { rst rst~out0 fre_div_factor[5] } { 0.000ns 0.000ns 1.178ns } { 0.000ns 1.469ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk fre_div_factor[5] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 fre_div_factor[5] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.514 ns" { rst fre_div_factor[5] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.514 ns" { rst rst~out0 fre_div_factor[5] } { 0.000ns 0.000ns 1.178ns } { 0.000ns 1.469ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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