fifo1.hif

学习UART知识

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1595
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
fifo1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fifo1.vhd
1180943004
4
# storage
db|fifo1.(0).cnf
db|fifo1.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
scfifo
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|scfifo.tdf
1114012440
6
# storage
db|fifo1.(1).cnf
db|fifo1.(1).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_DEC
USR
LPM_NUMWORDS
256
PARAMETER_DEC
USR
LPM_WIDTHU
8
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_skr
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clock
data0
data1
data2
data3
data4
data5
data6
data7
empty
full
q0
q1
q2
q3
q4
q5
q6
q7
rdreq
usedw0
usedw1
usedw2
usedw3
usedw4
usedw5
usedw6
usedw7
wrreq
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|a_regfifo.inc
1107572164
d:|altera|quartus50|libraries|megafunctions|a_dpfifo.inc
1107571908
d:|altera|quartus50|libraries|megafunctions|a_i2fifo.inc
1107572036
d:|altera|quartus50|libraries|megafunctions|a_fffifo.inc
1107571974
d:|altera|quartus50|libraries|megafunctions|a_f2fifo.inc
1107571944
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
}
# hierarchies {
scfifo:scfifo_component
}
# end
# entity
scfifo_skr
# case_insensitive
# source_file
db|scfifo_skr.tdf
1181354058
6
# storage
db|fifo1.(2).cnf
db|fifo1.(2).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
wrreq
rdreq
clock
aclr
q0
q1
q2
q3
q4
q5
q6
q7
empty
full
usedw0
usedw1
usedw2
usedw3
usedw4
usedw5
usedw6
usedw7
}
# hierarchies {
scfifo:scfifo_component|scfifo_skr:auto_generated
}
# end
# entity
a_dpfifo_3rr
# case_insensitive
# source_file
db|a_dpfifo_3rr.tdf
1181354058
6
# storage
db|fifo1.(3).cnf
db|fifo1.(3).cnf
# used_port {
aclr
clock
data0
data1
data2
data3
data4
data5
data6
data7
rreq
sclr
wreq
empty
full
q0
q1
q2
q3
q4
q5
q6
q7
usedw0
usedw1
usedw2
usedw3
usedw4
usedw5
usedw6
usedw7
}
# hierarchies {
scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo
}
# end
# entity
altsyncram_vf31
# case_insensitive
# source_file
db|altsyncram_vf31.tdf
1181354058
6
# storage
db|fifo1.(4).cnf
db|fifo1.(4).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
clock0
clock1
clocken1
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
wren_a
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
none
0
}
# hierarchies {
scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram
}
# end
# entity
cntr_sd8
# case_insensitive
# source_file
db|cntr_sd8.tdf
1181354058
6
# storage
db|fifo1.(5).cnf
db|fifo1.(5).cnf
# used_port {
aclr
clock
cnt_en
sclr
q0
q1
q2
q3
q4
q5
q6
}
# hierarchies {
scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|cntr_sd8:rd_ptr_msb
}
# end
# entity
cntr_bc7
# case_insensitive
# source_file
db|cntr_bc7.tdf
1181354058
6
# storage
db|fifo1.(6).cnf
db|fifo1.(6).cnf
# used_port {
aclr
clock
cnt_en
sclr
updown
q0
q1
q2
q3
q4
q5
q6
q7
}
# hierarchies {
scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|cntr_bc7:usedw_counter
}
# end
# entity
cntr_td8
# case_insensitive
# source_file
db|cntr_td8.tdf
1181354058
6
# storage
db|fifo1.(7).cnf
db|fifo1.(7).cnf
# used_port {
aclr
clock
cnt_en
sclr
q0
q1
q2
q3
q4
q5
q6
q7
}
# hierarchies {
scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|cntr_td8:wr_ptr
}
# end
# complete