fifo1.fit.qmsg

学习UART知识

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.319 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0 1 MEM M4K_X13_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[0\] 2 MEM M4K_X13_Y7 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[0\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.319 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[0] } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.319 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 09 09:54:28 2007 " "Info: Processing ended: Sat Jun 09 09:54:28 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}