fifo1.hier_info

学习UART知识

|fifo1
data[0] => scfifo:scfifo_component.data[0]
data[1] => scfifo:scfifo_component.data[1]
data[2] => scfifo:scfifo_component.data[2]
data[3] => scfifo:scfifo_component.data[3]
data[4] => scfifo:scfifo_component.data[4]
data[5] => scfifo:scfifo_component.data[5]
data[6] => scfifo:scfifo_component.data[6]
data[7] => scfifo:scfifo_component.data[7]
wrreq => scfifo:scfifo_component.wrreq
rdreq => scfifo:scfifo_component.rdreq
clock => scfifo:scfifo_component.clock
aclr => scfifo:scfifo_component.aclr
q[0] <= scfifo:scfifo_component.q[0]
q[1] <= scfifo:scfifo_component.q[1]
q[2] <= scfifo:scfifo_component.q[2]
q[3] <= scfifo:scfifo_component.q[3]
q[4] <= scfifo:scfifo_component.q[4]
q[5] <= scfifo:scfifo_component.q[5]
q[6] <= scfifo:scfifo_component.q[6]
q[7] <= scfifo:scfifo_component.q[7]
full <= scfifo:scfifo_component.full
empty <= scfifo:scfifo_component.empty
usedw[0] <= scfifo:scfifo_component.usedw[0]
usedw[1] <= scfifo:scfifo_component.usedw[1]
usedw[2] <= scfifo:scfifo_component.usedw[2]
usedw[3] <= scfifo:scfifo_component.usedw[3]
usedw[4] <= scfifo:scfifo_component.usedw[4]
usedw[5] <= scfifo:scfifo_component.usedw[5]
usedw[6] <= scfifo:scfifo_component.usedw[6]
usedw[7] <= scfifo:scfifo_component.usedw[7]


|fifo1|scfifo:scfifo_component
data[0] => scfifo_skr:auto_generated.data[0]
data[1] => scfifo_skr:auto_generated.data[1]
data[2] => scfifo_skr:auto_generated.data[2]
data[3] => scfifo_skr:auto_generated.data[3]
data[4] => scfifo_skr:auto_generated.data[4]
data[5] => scfifo_skr:auto_generated.data[5]
data[6] => scfifo_skr:auto_generated.data[6]
data[7] => scfifo_skr:auto_generated.data[7]
q[0] <= scfifo_skr:auto_generated.q[0]
q[1] <= scfifo_skr:auto_generated.q[1]
q[2] <= scfifo_skr:auto_generated.q[2]
q[3] <= scfifo_skr:auto_generated.q[3]
q[4] <= scfifo_skr:auto_generated.q[4]
q[5] <= scfifo_skr:auto_generated.q[5]
q[6] <= scfifo_skr:auto_generated.q[6]
q[7] <= scfifo_skr:auto_generated.q[7]
wrreq => scfifo_skr:auto_generated.wrreq
rdreq => scfifo_skr:auto_generated.rdreq
clock => scfifo_skr:auto_generated.clock
aclr => scfifo_skr:auto_generated.aclr
sclr => ~NO_FANOUT~
empty <= scfifo_skr:auto_generated.empty
full <= scfifo_skr:auto_generated.full
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= scfifo_skr:auto_generated.usedw[0]
usedw[1] <= scfifo_skr:auto_generated.usedw[1]
usedw[2] <= scfifo_skr:auto_generated.usedw[2]
usedw[3] <= scfifo_skr:auto_generated.usedw[3]
usedw[4] <= scfifo_skr:auto_generated.usedw[4]
usedw[5] <= scfifo_skr:auto_generated.usedw[5]
usedw[6] <= scfifo_skr:auto_generated.usedw[6]
usedw[7] <= scfifo_skr:auto_generated.usedw[7]


|fifo1|scfifo:scfifo_component|scfifo_skr:auto_generated
aclr => a_dpfifo_3rr:dpfifo.aclr
clock => a_dpfifo_3rr:dpfifo.clock
data[0] => a_dpfifo_3rr:dpfifo.data[0]
data[1] => a_dpfifo_3rr:dpfifo.data[1]
data[2] => a_dpfifo_3rr:dpfifo.data[2]
data[3] => a_dpfifo_3rr:dpfifo.data[3]
data[4] => a_dpfifo_3rr:dpfifo.data[4]
data[5] => a_dpfifo_3rr:dpfifo.data[5]
data[6] => a_dpfifo_3rr:dpfifo.data[6]
data[7] => a_dpfifo_3rr:dpfifo.data[7]
empty <= a_dpfifo_3rr:dpfifo.empty
full <= a_dpfifo_3rr:dpfifo.full
q[0] <= a_dpfifo_3rr:dpfifo.q[0]
q[1] <= a_dpfifo_3rr:dpfifo.q[1]
q[2] <= a_dpfifo_3rr:dpfifo.q[2]
q[3] <= a_dpfifo_3rr:dpfifo.q[3]
q[4] <= a_dpfifo_3rr:dpfifo.q[4]
q[5] <= a_dpfifo_3rr:dpfifo.q[5]
q[6] <= a_dpfifo_3rr:dpfifo.q[6]
q[7] <= a_dpfifo_3rr:dpfifo.q[7]
rdreq => a_dpfifo_3rr:dpfifo.rreq
usedw[0] <= a_dpfifo_3rr:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_3rr:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_3rr:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_3rr:dpfifo.usedw[3]
usedw[4] <= a_dpfifo_3rr:dpfifo.usedw[4]
usedw[5] <= a_dpfifo_3rr:dpfifo.usedw[5]
usedw[6] <= a_dpfifo_3rr:dpfifo.usedw[6]
usedw[7] <= a_dpfifo_3rr:dpfifo.usedw[7]
wrreq => a_dpfifo_3rr:dpfifo.wreq


|fifo1|scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo
aclr => cntr_sd8:rd_ptr_msb.aclr
aclr => cntr_bc7:usedw_counter.aclr
aclr => cntr_td8:wr_ptr.aclr
clock => altsyncram_vf31:FIFOram.clock0
clock => altsyncram_vf31:FIFOram.clock1
clock => cntr_sd8:rd_ptr_msb.clock
clock => cntr_bc7:usedw_counter.clock
clock => cntr_td8:wr_ptr.clock
clock => empty_dff.CLK
clock => full_dff.CLK
clock => low_addressa[7].CLK
clock => low_addressa[6].CLK
clock => low_addressa[5].CLK
clock => low_addressa[4].CLK
clock => low_addressa[3].CLK
clock => low_addressa[2].CLK
clock => low_addressa[1].CLK
clock => low_addressa[0].CLK
clock => rd_ptr_lsb.CLK
clock => usedw_is_0_dff.CLK
clock => usedw_is_1_dff.CLK
clock => wrreq_delay.CLK
data[0] => altsyncram_vf31:FIFOram.data_a[0]
data[1] => altsyncram_vf31:FIFOram.data_a[1]
data[2] => altsyncram_vf31:FIFOram.data_a[2]
data[3] => altsyncram_vf31:FIFOram.data_a[3]
data[4] => altsyncram_vf31:FIFOram.data_a[4]
data[5] => altsyncram_vf31:FIFOram.data_a[5]
data[6] => altsyncram_vf31:FIFOram.data_a[6]
data[7] => altsyncram_vf31:FIFOram.data_a[7]
empty <= empty_out.DB_MAX_OUTPUT_PORT_TYPE
full <= full_dff.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= altsyncram_vf31:FIFOram.q_b[0]
q[1] <= altsyncram_vf31:FIFOram.q_b[1]
q[2] <= altsyncram_vf31:FIFOram.q_b[2]
q[3] <= altsyncram_vf31:FIFOram.q_b[3]
q[4] <= altsyncram_vf31:FIFOram.q_b[4]
q[5] <= altsyncram_vf31:FIFOram.q_b[5]
q[6] <= altsyncram_vf31:FIFOram.q_b[6]
q[7] <= altsyncram_vf31:FIFOram.q_b[7]
rreq => valid_rreq.IN0
sclr => cntr_sd8:rd_ptr_msb.sclr
sclr => cntr_bc7:usedw_counter.sclr
sclr => cntr_td8:wr_ptr.sclr
usedw[0] <= cntr_bc7:usedw_counter.q[0]
usedw[1] <= cntr_bc7:usedw_counter.q[1]
usedw[2] <= cntr_bc7:usedw_counter.q[2]
usedw[3] <= cntr_bc7:usedw_counter.q[3]
usedw[4] <= cntr_bc7:usedw_counter.q[4]
usedw[5] <= cntr_bc7:usedw_counter.q[5]
usedw[6] <= cntr_bc7:usedw_counter.q[6]
usedw[7] <= cntr_bc7:usedw_counter.q[7]
wreq => valid_wreq.IN0


|fifo1|scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1