lwbsram.v

视频解压缩程序（用verilog语言实现）

/////////////////////////////////////////////////////////////////////
////                                                             ////
////             LWB rev 1.2 -- SRAM  INTERFACE                  ////
////                                                             ////
////                                                             ////
////                 Author: Liu Tao                             ////
////          [e-mail]                           ////
////                                                             ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////               Copyright (C) 2003 Liu Tao                    ////
////               [e-mail]                      ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

`include "timescale.v"

module LWBSRAM (reset,clk,doWrite,writeAddr,writeData,SRAM_CE_,SRAM_OE_,SRAM_WE_,SRAM_ADDR,SRAM_DATA);
	

	//=================================================================================
	//input
	//=================================================================================

	    /*___________________________________________________ */
		//reset
		input reset;//AS reset

	    /*___________________________________________________ */
		//clock
		input clk;//clock from saa7113 interface

		input doWrite;
		input [18:0] writeAddr;//address
		input [7:0] writeData;//data
		


	//=================================================================================
	//output
	//=================================================================================
	    /*___________________________________________________ */
		//output to SRAM
		output SRAM_CE_;
		output SRAM_OE_;
		output SRAM_WE_;

		output [18:0] SRAM_ADDR;
		output [7:0] SRAM_DATA;


	//=================================================================================
	//reg
	//=================================================================================
		reg SRAM_CE_;
		reg SRAM_OE_;
		reg SRAM_WE_;
		reg [18:0] SRAM_ADDR;
		reg [7:0] SRAM_DATA;

		reg [18:0] writeDataReg;//buffer for data
//		reg [18:0] writeAddrReg;//buffer for adder

		reg [1:0] presState;//state reg
		reg [1:0] nextState;


		reg regWriteAddr;
		reg regWriteData;

	//=================================================================================
	//parameters
	//=================================================================================
		parameter stIdle = 2'b00;
		parameter stWrite1 = 2'b01;
		parameter stWrite2 = 2'b10;


	//=================================================================================
	//assigning
	//=================================================================================



	//=================================================================================
	//Logic
	//=================================================================================

	    /*___________________________________________________ */
		//STATE MACHINE FOR write data
		always @(writeDataReg or presState or clk)
			if	(((presState == stWrite1) && (clk == 1'b0)) ||(presState == stWrite2))
				SRAM_DATA <= writeDataReg;
			else
				SRAM_DATA <= 8'hzz;


	    /*___________________________________________________ */
		//STATE MACHINE FOR output WE
		always @(presState or clk)
			if	(((presState == stWrite1) && (clk == 1'b0)) || ((presState == stWrite2) && (clk == 1'b1)))
				SRAM_WE_ <= 1'b0;
			else
				SRAM_WE_ <= 1'b1;

	    /*___________________________________________________ */
		//STATE MACHINE FOR get data and address from input
		always @(posedge clk or negedge reset)
			if(!reset)
				begin
//					nextState <= stIdle;
					presState <= stIdle;
					SRAM_CE_ <= 1'b1;

					SRAM_ADDR <= 8'h00; 
					writeDataReg <= 8'h00;

//					regWriteAddr <= 1'b0;
//					regWriteData <= 1'b0;

				end
			else
				begin
					SRAM_CE_ <= 1'b0;
		
					if (regWriteAddr == 1'b1 ) //Handle the clock-enabling of each register
						SRAM_ADDR <= writeAddr;

					if (regWriteData == 1'b1)  //Handle the clock-enabling of each register:
						writeDataReg <= writeData;

					presState <= nextState;
				end


	    /*___________________________________________________ */
		//STATE MACHINE FOR 
		always @(presState or doWrite)
			begin
				case (presState)
					stIdle://
						begin

							SRAM_OE_ <= 1'b0;
							regWriteAddr <= 1'b0;
							regWriteData <= 1'b0;

							nextState <= stIdle;

							if (doWrite == 1'b1)
								begin
									nextState <= stWrite1;
		
									regWriteAddr <= 1'b1;
									regWriteData <= 1'b1;
								end
						end
			
					stWrite1://
						begin
							nextState <= stWrite2;
							SRAM_OE_ <= 1'b1;
						end	

					stWrite2://
						begin
							nextState <= stIdle;

							if(doWrite == 1'b1)
								begin
									nextState <= stWrite1;
		
									regWriteAddr <= 1'b1;
									regWriteData <= 1'b1;					
								end

							SRAM_OE_ <= 1'b1;
						end
				endcase
			end

endmodule