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📄 mini-risc core _opencores_org.mht

📁 VERILOG VERSION PIC16C57 是一个用于FPGA模拟PIC16C57的IP核
💻 MHT
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                        <P>A very nice(and free) development environment =
with a=20
                        software simulator is provided by Microchip on =
their web=20
                        site. This environment works only on PCs. =
Various free=20
                        and chimerical tools are available from third =
party,=20
                        just Search the web !
                        <P><A=20
                        =
href=3D"http://www.microchip.com/10/Tools/PICmicro/DevEnv/">Here=20
                        is a link to the Microchip Development =
environment</A>=20
                        (<A=20
                        =
href=3D"http://www.microchip.com/10/Tools/PICmicro/DevEnv/">http://www.mi=
crochip.com/10/Tools/PICmicro/DevEnv/</A>)<BR>
                        <P><B><FONT class=3Dblock_title =
size=3D+1>To-Do</FONT></B>=20
                        <P>Things that need to be done
                        <P>1.Write more test/compliance test vectors =
<BR>
                        <UL>
                          <UL>
                            <LI>Verify that all instructions after a=20
                            goto/call/retlw/write to PCL are not =
executed=20
                            <LI>Verify ALU=20
                            <LI>Timer and Watchdog tests=20
                            <LI>Perhaps some other areas ?=20
                        </LI></UL></UL>2.Extensions ? <BR>
                        <UL>
                          <UL>
                            <LI>guess this is on a "as needed" basis=20
                            <LI>Would be nice to extend the register =
file and=20
                            have a few registers that are shared between =
two or=20
                            more of this cores in a MP implementation !=20
                        </LI></UL></UL>
                        <P><B><FONT class=3Dblock_title size=3D+1>Change =

                        log</FONT></B>=20
                        <P>6/18/200 RU <BR>
                        <UL>
                          <LI>Added this Change Log=20
                          <LI>Added "Development Tools" Section|=20
                          <LI>Removed speed claims from the =
"Performance"=20
                          Section: Need to re-synthsise the core and =
resolve=20
                          synthesis tool/backend tool issues.=20
                          <LI>added "risc_core_top.v", a top level with=20
                          tri-state buffers and program memory, to make =
it look=20
                          like a real PIC !=20
                          <LI>Updated the primitives_xilinx.v so it will =
work=20
                          correctly with Synplify and Synopsys FPGA=20
                        compiler</LI></UL>
                        <P><B><FONT class=3Dblock_title =
size=3D+1><BR><BR><FONT=20
                        size=3D-1>This IP Core is provided =
by:</FONT></FONT></B>=20
                        <P>
                        <P align=3Dcenter><B><FONT class=3Dblock_title =
size=3D+1><FONT=20
                        color=3Dred><BR>www.ASICS.ws - Solutions for =
your=20
                        ASIC/FPGA needs - <BR></FONT></B></P><BR>
                        <P><BR>&nbsp; <!-- pf_body_end =
--></P></FONT></TD>
                      <TD><IMG =
src=3D"http://www.opencores.org/images/dotty.gif"=20
                        width=3D15></TD></TR></TBODY></TABLE><!-- =
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</TD></TR>
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bgColor=3D#b3b3b3=20
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        <TR>
          <TD align=3Dright>Copyright (c) 1999
            <SCRIPT language=3DJavaScript>=0A=
           RightNow =3D new Date();=0A=
           document.write(" - " + RightNow.getFullYear());=0A=
         </SCRIPT>
             OPENCORES.ORG. All rights reserved. &nbsp; </TD></TR>
        <TR>
          <TD>&nbsp; </TD></TR></TBODY></TABLE></TD>
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width=3D1></TD></TR></TBODY></TABLE></CENTER><!-- pf_footer_start =
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