📄 std_2s60.v
字号:
cpu_data_master_qualified_request_seven_seg_pio_s1,
cpu_data_master_qualified_request_sys_clk_timer_s1,
cpu_data_master_qualified_request_sys_pll_s1,
cpu_data_master_qualified_request_sysid_control_slave,
cpu_data_master_qualified_request_vga_controller_0_s1,
cpu_data_master_qualified_request_vga_pll_s1,
cpu_data_master_read,
cpu_data_master_read_data_valid_button_pio_s1,
cpu_data_master_read_data_valid_cpu_jtag_debug_module,
cpu_data_master_read_data_valid_ext_flash_s1,
cpu_data_master_read_data_valid_ext_ram_s1,
cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
cpu_data_master_read_data_valid_led_pio_s1,
cpu_data_master_read_data_valid_profiling_timer_s1,
cpu_data_master_read_data_valid_sdram_s1,
cpu_data_master_read_data_valid_sdram_s1_shift_register,
cpu_data_master_read_data_valid_seven_seg_pio_s1,
cpu_data_master_read_data_valid_sys_clk_timer_s1,
cpu_data_master_read_data_valid_sys_pll_s1,
cpu_data_master_read_data_valid_sysid_control_slave,
cpu_data_master_read_data_valid_vga_controller_0_s1,
cpu_data_master_read_data_valid_vga_pll_s1,
cpu_data_master_requests_button_pio_s1,
cpu_data_master_requests_cpu_jtag_debug_module,
cpu_data_master_requests_ext_flash_s1,
cpu_data_master_requests_ext_ram_s1,
cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
cpu_data_master_requests_led_pio_s1,
cpu_data_master_requests_profiling_timer_s1,
cpu_data_master_requests_sdram_s1,
cpu_data_master_requests_seven_seg_pio_s1,
cpu_data_master_requests_sys_clk_timer_s1,
cpu_data_master_requests_sys_pll_s1,
cpu_data_master_requests_sysid_control_slave,
cpu_data_master_requests_vga_controller_0_s1,
cpu_data_master_requests_vga_pll_s1,
cpu_data_master_write,
cpu_data_master_writedata,
cpu_jtag_debug_module_readdata_from_sa,
d1_button_pio_s1_end_xfer,
d1_cpu_jtag_debug_module_end_xfer,
d1_ext_ram_bus_avalon_slave_end_xfer,
d1_jtag_uart_avalon_jtag_slave_end_xfer,
d1_led_pio_s1_end_xfer,
d1_profiling_timer_s1_end_xfer,
d1_sdram_s1_end_xfer,
d1_seven_seg_pio_s1_end_xfer,
d1_sys_clk_timer_s1_end_xfer,
d1_sys_pll_s1_end_xfer,
d1_sysid_control_slave_end_xfer,
d1_vga_controller_0_s1_end_xfer,
d1_vga_pll_s1_end_xfer,
ext_flash_s1_wait_counter_eq_0,
ext_flash_s1_wait_counter_eq_1,
ext_ram_s1_wait_counter_eq_0,
ext_ram_s1_wait_counter_eq_1,
incoming_ext_ram_bus_data,
incoming_ext_ram_bus_data_with_Xs_converted_to_0,
jtag_uart_avalon_jtag_slave_irq_from_sa,
jtag_uart_avalon_jtag_slave_readdata_from_sa,
jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
profiling_timer_s1_irq_from_sa,
profiling_timer_s1_readdata_from_sa,
registered_cpu_data_master_read_data_valid_ext_flash_s1,
registered_cpu_data_master_read_data_valid_ext_ram_s1,
reset_n,
sdram_s1_readdata_from_sa,
sdram_s1_waitrequest_from_sa,
sys_clk_timer_s1_irq_from_sa,
sys_clk_timer_s1_readdata_from_sa,
sys_pll_s1_readdata_from_sa,
sysid_control_slave_readdata_from_sa,
vga_controller_0_s1_readdata_from_sa,
vga_pll_s1_readdata_from_sa,
// outputs:
cpu_data_master_address_to_slave,
cpu_data_master_dbs_address,
cpu_data_master_dbs_write_8,
cpu_data_master_irq,
cpu_data_master_no_byte_enables_and_last_term,
cpu_data_master_readdata,
cpu_data_master_waitrequest
)
/* synthesis auto_dissolve = "FALSE" */ ;
output [ 25: 0] cpu_data_master_address_to_slave;
output [ 1: 0] cpu_data_master_dbs_address;
output [ 7: 0] cpu_data_master_dbs_write_8;
output [ 31: 0] cpu_data_master_irq;
output cpu_data_master_no_byte_enables_and_last_term;
output [ 31: 0] cpu_data_master_readdata;
output cpu_data_master_waitrequest;
input button_pio_s1_irq_from_sa;
input [ 3: 0] button_pio_s1_readdata_from_sa;
input clk;
input [ 25: 0] cpu_data_master_address;
input cpu_data_master_byteenable_ext_flash_s1;
input cpu_data_master_debugaccess;
input cpu_data_master_granted_button_pio_s1;
input cpu_data_master_granted_cpu_jtag_debug_module;
input cpu_data_master_granted_ext_flash_s1;
input cpu_data_master_granted_ext_ram_s1;
input cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
input cpu_data_master_granted_led_pio_s1;
input cpu_data_master_granted_profiling_timer_s1;
input cpu_data_master_granted_sdram_s1;
input cpu_data_master_granted_seven_seg_pio_s1;
input cpu_data_master_granted_sys_clk_timer_s1;
input cpu_data_master_granted_sys_pll_s1;
input cpu_data_master_granted_sysid_control_slave;
input cpu_data_master_granted_vga_controller_0_s1;
input cpu_data_master_granted_vga_pll_s1;
input cpu_data_master_qualified_request_button_pio_s1;
input cpu_data_master_qualified_request_cpu_jtag_debug_module;
input cpu_data_master_qualified_request_ext_flash_s1;
input cpu_data_master_qualified_request_ext_ram_s1;
input cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
input cpu_data_master_qualified_request_led_pio_s1;
input cpu_data_master_qualified_request_profiling_timer_s1;
input cpu_data_master_qualified_request_sdram_s1;
input cpu_data_master_qualified_request_seven_seg_pio_s1;
input cpu_data_master_qualified_request_sys_clk_timer_s1;
input cpu_data_master_qualified_request_sys_pll_s1;
input cpu_data_master_qualified_request_sysid_control_slave;
input cpu_data_master_qualified_request_vga_controller_0_s1;
input cpu_data_master_qualified_request_vga_pll_s1;
input cpu_data_master_read;
input cpu_data_master_read_data_valid_button_pio_s1;
input cpu_data_master_read_data_valid_cpu_jtag_debug_module;
input cpu_data_master_read_data_valid_ext_flash_s1;
input cpu_data_master_read_data_valid_ext_ram_s1;
input cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
input cpu_data_master_read_data_valid_led_pio_s1;
input cpu_data_master_read_data_valid_profiling_timer_s1;
input cpu_data_master_read_data_valid_sdram_s1;
input cpu_data_master_read_data_valid_sdram_s1_shift_register;
input cpu_data_master_read_data_valid_seven_seg_pio_s1;
input cpu_data_master_read_data_valid_sys_clk_timer_s1;
input cpu_data_master_read_data_valid_sys_pll_s1;
input cpu_data_master_read_data_valid_sysid_control_slave;
input cpu_data_master_read_data_valid_vga_controller_0_s1;
input cpu_data_master_read_data_valid_vga_pll_s1;
input cpu_data_master_requests_button_pio_s1;
input cpu_data_master_requests_cpu_jtag_debug_module;
input cpu_data_master_requests_ext_flash_s1;
input cpu_data_master_requests_ext_ram_s1;
input cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
input cpu_data_master_requests_led_pio_s1;
input cpu_data_master_requests_profiling_timer_s1;
input cpu_data_master_requests_sdram_s1;
input cpu_data_master_requests_seven_seg_pio_s1;
input cpu_data_master_requests_sys_clk_timer_s1;
input cpu_data_master_requests_sys_pll_s1;
input cpu_data_master_requests_sysid_control_slave;
input cpu_data_master_requests_vga_controller_0_s1;
input cpu_data_master_requests_vga_pll_s1;
input cpu_data_master_write;
input [ 31: 0] cpu_data_master_writedata;
input [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
input d1_button_pio_s1_end_xfer;
input d1_cpu_jtag_debug_module_end_xfer;
input d1_ext_ram_bus_avalon_slave_end_xfer;
input d1_jtag_uart_avalon_jtag_slave_end_xfer;
input d1_led_pio_s1_end_xfer;
input d1_profiling_timer_s1_end_xfer;
input d1_sdram_s1_end_xfer;
input d1_seven_seg_pio_s1_end_xfer;
input d1_sys_clk_timer_s1_end_xfer;
input d1_sys_pll_s1_end_xfer;
input d1_sysid_control_slave_end_xfer;
input d1_vga_controller_0_s1_end_xfer;
input d1_vga_pll_s1_end_xfer;
input ext_flash_s1_wait_counter_eq_0;
input ext_flash_s1_wait_counter_eq_1;
input ext_ram_s1_wait_counter_eq_0;
input ext_ram_s1_wait_counter_eq_1;
input [ 31: 0] incoming_ext_ram_bus_data;
input [ 7: 0] incoming_ext_ram_bus_data_with_Xs_converted_to_0;
input jtag_uart_avalon_jtag_slave_irq_from_sa;
input [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
input jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
input profiling_timer_s1_irq_from_sa;
input [ 15: 0] profiling_timer_s1_readdata_from_sa;
input registered_cpu_data_master_read_data_valid_ext_flash_s1;
input registered_cpu_data_master_read_data_valid_ext_ram_s1;
input reset_n;
input [ 31: 0] sdram_s1_readdata_from_sa;
input sdram_s1_waitrequest_from_sa;
input sys_clk_timer_s1_irq_from_sa;
input [ 15: 0] sys_clk_timer_s1_readdata_from_sa;
input [ 15: 0] sys_pll_s1_readdata_from_sa;
input [ 31: 0] sysid_control_slave_readdata_from_sa;
input [ 31: 0] vga_controller_0_s1_readdata_from_sa;
input [ 15: 0] vga_pll_s1_readdata_from_sa;
wire [ 25: 0] cpu_data_master_address_to_slave;
reg [ 1: 0] cpu_data_master_dbs_address;
wire [ 1: 0] cpu_data_master_dbs_increment;
wire [ 7: 0] cpu_data_master_dbs_write_8;
wire [ 31: 0] cpu_data_master_irq;
reg cpu_data_master_no_byte_enables_and_last_term;
wire [ 31: 0] cpu_data_master_readdata;
wire cpu_data_master_run;
reg cpu_data_master_waitrequest;
reg [ 7: 0] dbs_8_reg_segment_0;
reg [ 7: 0] dbs_8_reg_segment_1;
reg [ 7: 0] dbs_8_reg_segment_2;
wire dbs_count_enable;
wire dbs_counter_overflow;
wire last_dbs_term_and_run;
wire [ 1: 0] next_dbs_address;
wire [ 7: 0] p1_dbs_8_reg_segment_0;
wire [ 7: 0] p1_dbs_8_reg_segment_1;
wire [ 7: 0] p1_dbs_8_reg_segment_2;
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