_primary.vhd

来自「wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity wb_mast is
    generic(
        mem_size        : integer := 4096
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        adr             : out    vl_logic_vector(31 downto 0);
        din             : in     vl_logic_vector(31 downto 0);
        dout            : out    vl_logic_vector(31 downto 0);
        cyc             : out    vl_logic;
        stb             : out    vl_logic;
        sel             : out    vl_logic_vector(3 downto 0);
        we              : out    vl_logic;
        ack             : in     vl_logic;
        err             : in     vl_logic;
        rty             : in     vl_logic
    );
end wb_mast;