locker.v

来自「handshake checker and it is used in the 」· Verilog 代码 · 共 27 行

/*module locker;
    wire reset;
    wire e0;
    reg ef;
    always
    begin
    
    if(e0==1&&reset==1) ef<=0;
    else if (reset==1) ef<=0;
    else if (e0==1) ef<=1;
   end
   endmodule */
   

   module locker(reset,e0,ef);
    input reset;
    input e0;
    output ef;
	reg ef;
    always@(reset or e0)
    begin
    
    if(e0==1&&reset==1) ef<=0;
    else if (reset==1) ef<=0;
    else if (e0==1) ef<=1;
   end
   endmodule