d_ff.v

来自「handshake checker and it is used in the 」· Verilog 代码 · 共 24 行

/*module d_ff;
wire d,clk;
reg q,_q;
always@(posedge clk)
begin
    q<=d;
    _q<=~d;
end
endmodule */




module d_ff(clk,d,q,_q);
input d,clk;

output q,_q;
reg q,_q;
always@(posedge clk)
begin
    q<=d;
    _q<=~d;
end
endmodule