handshake_gate_t.v

来自「handshake checker and it is used in the 」· Verilog 代码 · 共 20 行

module handshake_t();
reg clk,r,a,reset;
wire ef;
handshake_gate C (a,clk,r,reset,ef);
initial 
 begin
  clk=0;r=0;a=0;reset=0;
  #30 r=1;
  #20 a=1;
  #60 r=0;
  #20 a=0;
  #50 a=1;
  #10 reset=1;
  #10 r=1;
  #20 $stop;
 end
always #5 clk=~clk;
endmodule