rest_div_int.v

a divider design based on verilog language

module rest_div_int(X, Y, Q, R);
	parameter N = 8,
			  M = 8;	
	input [M-1:0]	X;
	input [N-1:0] 	Y;
	output[M-1:0]	Q;
	output[N-1:0]	R;
	
	reg [N:0] wire_in[M-1:0], wire_out[M-1:0];
	reg [N-1:0] zeros;
	reg [M-1:0] Q;
	reg [N-1:0] R;	
	always @(X or Y)begin:DIVIDER
		integer i;
		zeros = 0;
		wire_in[0] = {zeros, X[M-1]};
		for(i=0; i<=M-1; i=i+1)begin
			rst_div_cell(wire_in[i],		// 调用基本单元
						Y, 
						Q[M-i-1], 
						wire_out[i][N-1:0]);
		end
		for(i=0; i<=M-2; i=i+1)
			wire_in[i+1] = {wire_out[i][N-1:0], X[M-i-2]};
		R = wire_out[M-1][N-1:0];
	end
	
	// 用任务描述的基本单元
	task rst_div_cell(input [N:0] 	a_by_2,
					  input [N-1:0]	b,
					  output		q,
					  output[N-1:0]	r);
		reg [N:0] subst;
		begin
			subst = a_by_2 - b;
			if(subst[N])	r = a_by_2[N-1:0];
			else			r = subst[N-1:0];
			q = !subst[N];		
		end
	endtask
endmodule