slave_floor_select.tan.qmsg

完整的九层电梯控制器verilog源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 07 20:28:04 2006 " "Info: Processing started: Mon Aug 07 20:28:04 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Slave_Floor_Select -c Slave_Floor_Select " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Slave_Floor_Select -c Slave_Floor_Select" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "CNT1\[4\]~15 " "Info: Node \"CNT1\[4\]~15\"" {  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 19 -1 0 } }  } 0}  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 19 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "CNT2\[4\]~15 " "Info: Node \"CNT2\[4\]~15\"" {  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 19 -1 0 } }  } 0}  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 19 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Down_Request Slave_Floor\[4\] 16.800 ns Longest " "Info: Longest tpd from source pin \"Down_Request\" to destination pin \"Slave_Floor\[4\]\" is 16.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Down_Request 1 PIN PIN_73 4 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_73; Fanout = 4; PIN Node = 'Down_Request'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "" { Down_Request } "NODE_NAME" } "" } } { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.800 ns) 5.600 ns always0~42 2 COMB LC5 3 " "Info: 2: + IC(1.600 ns) + CELL(3.800 ns) = 5.600 ns; Loc. = LC5; Fanout = 3; COMB Node = 'always0~42'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "5.400 ns" { Down_Request always0~42 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.400 ns) 11.000 ns CNT1\[4\]~15 3 COMB LOOP LC2 4 " "Info: 3: + IC(0.000 ns) + CELL(5.400 ns) = 11.000 ns; Loc. = LC2; Fanout = 4; COMB LOOP Node = 'CNT1\[4\]~15'" { { "Info" "ITDB_PART_OF_SCC" "CNT1\[4\]~15 LC2 " "Info: Loc. = LC2; Node \"CNT1\[4\]~15\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "" { CNT1[4]~15 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "" { CNT1[4]~15 } "NODE_NAME" } "" } } { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 19 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "5.400 ns" { always0~42 CNT1[4]~15 } "NODE_NAME" } "" } } { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.800 ns) 16.400 ns Slave_Floor~61 4 COMB LC8 1 " "Info: 4: + IC(1.600 ns) + CELL(3.800 ns) = 16.400 ns; Loc. = LC8; Fanout = 1; COMB Node = 'Slave_Floor~61'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "5.400 ns" { CNT1[4]~15 Slave_Floor~61 } "NODE_NAME" } "" } } { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 16.800 ns Slave_Floor\[4\] 5 PIN PIN_9 0 " "Info: 5: + IC(0.000 ns) + CELL(0.400 ns) = 16.800 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'Slave_Floor\[4\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "0.400 ns" { Slave_Floor~61 Slave_Floor[4] } "NODE_NAME" } "" } } { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/Slave_Floor_Select.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns 80.95 % " "Info: Total cell delay = 13.600 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns 19.05 % " "Info: Total interconnect delay = 3.200 ns ( 19.05 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select_cmp.qrpt" Compiler "Slave_Floor_Select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/db/Slave_Floor_Select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Floor_Select/" "" "16.800 ns" { Down_Request always0~42 CNT1[4]~15 Slave_Floor~61 Slave_Floor[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.800 ns" { Down_Request Down_Request~out always0~42 CNT1[4]~15 Slave_Floor~61 Slave_Floor[4] } { 0.000ns 0.000ns 1.600ns 0.000ns 1.600ns 0.000ns } { 0.000ns 0.200ns 3.800ns 5.400ns 3.800ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 07 20:28:04 2006 " "Info: Processing ended: Mon Aug 07 20:28:04 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}