forward.v

MIPS CPU tested in Icarus Verilog

module ForwardUnit (Clock, Reset, AddressA, AddressB, ExDest, MemDest, WbDest, DecEx_WrRF, ExMem_WrRF, MemWb_WrRF,
		    Forward1, Forward2);

   // ---------------------------- Input ports ----------------------------
   input Clock;
   input Reset;
   input AddressA;
   input AddressB;
   input ExDest;
   input MemDest;
   input WbDest;
   input DecEx_WrRF;
   input ExMem_WrRF;
   input MemWb_WrRF;

   // ---------------------------- Output ports ----------------------------
   output Forward1;
   output Forward2;

   // Constants
   parameter AddressWidth = 5;

   // ---------------------------- Type of Input ports ----------------------------
   wire Clock;
   wire Reset;
   wire [AddressWidth-1:0] AddressA;
   wire [AddressWidth-1:0] AddressB;
   wire [AddressWidth-1:0] ExDest;
   wire [AddressWidth-1:0] MemDest;
   wire [AddressWidth-1:0] WbDest;
   wire 		   DecEx_WrRF;
   wire 		   ExMem_WrRF;
   wire 		   MemWb_WrRF;

   // ---------------------------- Type of Output ports ----------------------------
   reg [1:0]		   Forward1;
   reg [1:0]		   Forward2;

   reg 		   fw1;
   reg 		   fw2;

   always @ (posedge Clock)
     begin
	fw1 = 0;
	fw2 = 0;
	if (Reset == 1'b1)
	  begin
	     Forward1 = 2'b00;
	     Forward2 = 2'b00;
	  end
	else
	  begin
	     if ((AddressA == WbDest) && (MemWb_WrRF == 1'b1))
	       begin
		  Forward1 = 2'b11;
		  fw1 = 1;
	       end
	     else
	       begin
	       end
	     if ((AddressA == MemDest) && (ExMem_WrRF == 1'b1))
	       begin
		  Forward1 = 2'b10;
		  fw1 = 1;
	       end
	     else
	       begin
	       end
	     if ((AddressA == ExDest) && (DecEx_WrRF == 1'b1))
	       begin
		  Forward1 = 2'b01;
		  fw1 = 1;
	       end
	     else
	       begin
	       end

	     if ((AddressB == WbDest) && (MemWb_WrRF == 1'b1))
	       begin
		  Forward2 = 2'b11;
		  fw2 = 1;
	       end
	     else
	       begin
	       end
	     if ((AddressB == MemDest) && (ExMem_WrRF == 1'b1))
	       begin
		  Forward2 = 2'b10;
		  fw2 = 1;
	       end
	     else
	       begin
	       end
	     if ((AddressB == ExDest) && (DecEx_WrRF == 1'b1))
	       begin
		  Forward2 = 2'b01;
		  fw2 = 1;
	       end
	     else
	       begin
	       end
	     if (fw1 == 0)
	       begin
		  Forward1 = 2'b00;
	       end
	     if (fw2 == 0)
	       begin
		  Forward2 = 2'b00;
	       end
	  end // else: !if(Reset == 1'b1)
     end // always @ (posedge Clock)
endmodule // ForwardUnit