cache.v

MIPS CPU tested in Icarus Verilog

module Cache (Clock, Reset, Write, Data_in, Data_out, Hit);

   parameter DATAWIDTH = 32; //Width of data
   parameter INDEX = 12; //2^12 = 4k lines of 2 sets (1 word/set)

   // ---------------------------- Input ports ----------------------------
   input Clock;
   input Reset;
   input Write; //Write to Cache?
   input Data_in; //Input Data

   // ---------------------------- Output ports ----------------------------
   output Data_out; //Output Data
   output Hit; //Hit?

   // ---------------------------- Type of Input ports ----------------------------
   wire Clock;
   wire Reset;
   wire Write; //Write signal
   wire [DATAWIDTH-1:0]       Data_in;
   wire [INDEX-1:0] 	      Index;
   wire [DATAWIDTH-INDEX-1:0] Tag_in;
   wire 		      Valid_in;

   // ---------------------------- Type of Output ports ----------------------------
   reg [DATAWIDTH-1:0] 	      Data_out;
   reg 			      Hit;
   reg [DATAWIDTH-INDEX-1:0]  Tag_out;
   reg 			      Valid;

   reg [0:4095] 	      LRU; //Least recently used set in a line;
   reg [105:0] 		      TEMPO;

   parameter 		      SIZE = 53; // Valid + Tag + Data

   reg [SIZE*2-1:0] 	      memcache [0:4095]; //Lines 0-4095

   integer 		      i;

   assign 		      Tag_in = Data_in[DATAWIDTH-1:INDEX];
   assign 		      Index = Data_in[INDEX-1:0];
   assign 		      Valid_in = (Index < 4096) ? 1 : 0;

   always @ (posedge Clock)
     begin
	if(Reset == 1'b1)
	  begin
	     for(i=0;i<4096;i=i+1)
	       begin
		  memcache[i] = 0;
		  LRU[i] = 0;
	       end
	  end
	else
	  begin
	     if(Write == 1'b1)
	       begin
		  if(LRU[Index] == 1'b0) //Write on the least recently used item
		    begin
		       //Tag_out = memcache[51:32][Index];
		       TEMPO = memcache[Index];
		       Tag_out = TEMPO[104:85];
		       Hit = (Tag_in == Tag_out);
		       //Tag_in = Tag_out;
		       //memcache[52:0][Index] = {Valid_in, Tag_in, Data_in};
		       TEMPO[105:53] = {Valid_in, Tag_out, Data_in};
		       memcache[Index] = TEMPO;
		       Data_out = Data_in;
		    end
		  else
		    begin
		       TEMPO = memcache[Index];
		       Tag_out = TEMPO[51:32];
		       Hit = (Tag_in == Tag_out);
		       //Tag_in = Tag_out;
		       TEMPO[52:0] = {Valid_in, Tag_out, Data_in};
		       Data_out = Data_in;
		    end // else: !if(LRU[Index] == 1'b0)
		  LRU[Index] = ~LRU[Index];
	       end // if (Write == 1'b1)
	     else // Write = 0, Read from cache
	       begin
		  if(LRU[Index] == 1'b1) //Read least least recently element
		    begin
		       TEMPO = memcache[Index];
		       Data_out = TEMPO[84:53];
		       Tag_out = TEMPO[104:85];
		       Valid = TEMPO[105];
		       Hit = (Tag_in == Tag_out);
		    end
		  else
		    begin
		       TEMPO = memcache[Index];
		       Data_out = TEMPO[31:0];
		       Tag_out = TEMPO[51:32];
		       Valid = TEMPO[52];
		       Hit = (Tag_in == Tag_out);
		    end // else: !if(LRU[Index] == 1'b1)
		  LRU[Index] = ~LRU[Index];
	       end // else: !if(Write == 1'b1)
	  end // else: !if(Reset == 1'b1)
     end // always @ (posedge Clock)
endmodule // Cache