muxes.v

MIPS CPU tested in Icarus Verilog

module MUX_2_1 (AInput, BInput, Select, Output);
   
   parameter DATALENGTH = 32;
   
   // --------------------------- Input Ports --------------------------
   input AInput;
   input BInput;
   input Select;

   // -------------------------- Output Ports --------------------------
   output Output;

   // -------------------------- Type of Input Ports --------------------------
   wire [DATALENGTH-1:0] AInput;
   wire [DATALENGTH-1:0] BInput;
   wire 		 Select;

   // -------------------------- Type of Output Ports --------------------------
   reg [DATALENGTH-1:0]  Output;

   always @ (AInput or BInput or Select)
     begin
	Output = (Select == 0) ? AInput : BInput;
     end
endmodule // MUX_2_1

module MUX_3_1 (AInput, BInput, CInput, Select, Output);

   parameter DATALENGTH = 32;
   
   // --------------------------- Input Ports --------------------------
   input AInput;
   input BInput;
   input CInput;
   input Select;

   // -------------------------- Output Ports --------------------------
   output Output;

   // -------------------------- Type of Input Ports --------------------------
   wire [DATALENGTH-1:0] AInput;
   wire [DATALENGTH-1:0] BInput;
   wire [DATALENGTH-1:0] CInput;
   wire [1:0] 		 Select;

   // -------------------------- Type of Output Ports --------------------------
   reg [DATALENGTH-1:0]  Output;

   always @ (AInput or BInput or CInput or Select)
     begin
	case(Select)
	  2'd0: begin
	     Output = AInput;
	  end
	  2'd1: begin
	     Output = BInput;
	  end
	  2'd2: begin
	     Output = CInput;
	  end
	  default: begin
	     Output = AInput;
	  end
	endcase // case(Select)
     end // always @ (posedge Clock)
endmodule // MUX_3_1

module MUX_4_1 (AInput, BInput, CInput, DInput, Select, Output);

   parameter DATALENGTH = 32;
   
   // --------------------------- Input Ports --------------------------
   input AInput;
   input BInput;
   input CInput;
   input DInput;
   input Select;

   // -------------------------- Output Ports --------------------------
   output Output;

   // -------------------------- Type of Input Ports --------------------------
   wire [DATALENGTH-1:0] AInput;
   wire [DATALENGTH-1:0] BInput;
   wire [DATALENGTH-1:0] CInput;
   wire [DATALENGTH-1:0] DInput;
   wire [1:0] 		 Select;

   // -------------------------- Type of Output Ports --------------------------
   reg [DATALENGTH-1:0]  Output;

   always @ (AInput or BInput or CInput or DInput or Select)
     begin
	case(Select)
	  2'd0: begin
	     Output = AInput;
	  end
	  2'd1: begin
	     Output = BInput;
	  end
	  2'd2: begin
	     Output = CInput;
	  end
	  2'd3: begin
	     Output = DInput;
	  end
	endcase // case(Select)
     end // always @ (posedge Clock)
endmodule // MUX_4_1

module MUX_6_1 (AInput, BInput, CInput, DInput, EInput, FInput, Select, Output);

   parameter DATALENGTH = 32;
   
   // --------------------------- Input Ports --------------------------
   input AInput;
   input BInput;
   input CInput;
   input DInput;
   input EInput;
   input FInput;
   input Select;

   // -------------------------- Output Ports --------------------------
   output Output;

   // -------------------------- Type of Input Ports --------------------------
   wire [DATALENGTH-1:0] AInput;
   wire [DATALENGTH-1:0] BInput;
   wire [DATALENGTH-1:0] CInput;
   wire [DATALENGTH-1:0] DInput;
   wire [DATALENGTH-1:0] EInput;
   wire [DATALENGTH-1:0] FInput;
   wire [2:0] 		 Select;

   // -------------------------- Type of Output Ports --------------------------
   reg [DATALENGTH-1:0]  Output;

   always @ (AInput or BInput or CInput or DInput or EInput or FInput or Select)
     begin
	case(Select)
	  3'd0: begin
	     Output = AInput;
	  end
	  3'd1: begin
	     Output = BInput;
	  end
	  3'd2: begin
	     Output = CInput;
	  end
	  3'd3: begin
	     Output = DInput;
	  end
	  3'd4: begin
	     Output = EInput;
	  end
	  3'd5: begin
	     Output = FInput;
	  end
	  default: begin
	     Output = AInput;
	  end
	endcase // case(Select)
     end // always @ (posedge Clock)
endmodule // MUX_6_1