alu_tb.v

MIPS CPU tested in Icarus Verilog

//----------------------------------------------------------------------------
//
// File Name:   alu_tb.v
//
// Type:        Test bench
//
// Description: This is the test bench for the 32-bit alu module. The test
//              bench excercises the following instructions:
//
//              ADD, ADDU, SUB, SUBU, MULT, MULTU, DIV, DIVU, AND, OR, XOR,
//              NOR, SLL, SRL, and SRA
//
//              All instructions operate on two sources and produce a result.
//
// Author:      Abelardo L髉ez Lagunas
//
//----------------------------------------------------------------------------
// Release history
//
// Version  Date      Description  
//   1.0    02/10/06  File created
//
//----------------------------------------------------------------------------
//
// Keywords: ALU test bench
//
//----------------------------------------------------------------------------
//
// Include the design under test below
`include "alu.v"
//
// Test bench code starts here
//
module alu_tb();

   // Declare inputs as regs and outputs as wires
   
   reg [31:0] AInput, BInput;
   reg [5:0]  OpCode;
   reg 		  Clock;
   reg 		  Reset;
   
   wire [31:0] Output;
   wire 	   Overfow;
   wire 	   Zero;

   //
   // Include the definition of all the ALU operations
   //
`include "Operations.v"
   
   // Initialize all variables
   initial begin
	  $dumpfile ("alu.vcd");
	  
	  // For now, dump all variables of the design
	  $dumpvars;
	  	  	  
	  Clock = 1'b1;        // initial value of clock
	  Reset = 1'b1;
	  OpCode = NOP;
	  
	  #10 Reset = 1'b0;
	  //
	  // Test the ADD instruction
	  //
	  #20 OpCode = S_ADD;
	  AInput = 32'hE000000A;
	  BInput = 32'h2000000A;
	  //
	  // Test the ADD instruction
	  //
	  #20 OpCode = S_ADD;
	  $display ("ADD\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h7FFFFFFF;
	  BInput = 32'h7000000A;
 	  //
	  // Test the ADDU instruction
	  //
	  #20 OpCode = S_ADDU;
	  $display ("ADD\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h7FFFFFFF;
	  BInput = 32'h7000000A;
	  //
	  // Test the SUB instruction
	  //
	  #20 OpCode = S_SUB;
	  $display ("ADDU\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'hE000000A;
	  BInput = 32'hE000000A;
	  //
	  // Test an overflow condition in the SUB instruction
	  //
	  #20 OpCode = S_SUB;
	  $display ("SUB\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h1000000A;
	  BInput = 32'hE000000A;
	  //
	  // Test the SUBU instruction
	  //
	  #20 OpCode = S_SUBU;
	  $display ("SUB\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'hE000000A;
	  BInput = 32'h1000000A;
	  //
	  // Test the MULT instruction
	  //
	  #20 OpCode = S_MULT;
	  $display ("SUBU\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000000A;
	  BInput = 32'h0001000A;
	  //
	  // Test the overflow condition in the MULT instruction
	  //
	  #20 OpCode = S_MULT;
	  $display ("MULT\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0002F00A;
	  BInput = 32'h000F000A;
	  //
	  // Test the MULTU instruction
	  //
	  #20 OpCode = S_MULTU;
	  $display ("MULT\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000000A;
	  BInput = 32'h0001000A;
	  //
	  // Test the DIV instruction
	  //
	  #20 OpCode = S_DIV;
	  $display ("MULTU\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
          AInput = 32'hFFFFFFFA;
	  BInput = 32'h00000002;
	  //
	  // Test the DIV instruction
	  //
	  #20 OpCode = S_DIV;
	  $display ("DIV\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0FFFFFFA;
	  BInput = 32'hFFFFFFFE;
	  //
	  // Test the DIVU instruction
	  //
	  #20 OpCode = S_DIVU;
	  $display ("DIV\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000000A;
	  BInput = 32'h00000002;
	  //
	  // Test the AND instruction
	  //
	  #20 OpCode = S_AND;
	  $display ("DIVU\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000000A;
	  BInput = 32'h0001000A;
	  //
	  // Test the OR instruction
	  //
	  #20 OpCode = S_OR;
	  $display ("AND\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000000A;
	  BInput = 32'hF0F0F0F0;
	  //
	  // Test the XOR instruction
	  //
	  #20 OpCode = S_XOR;
	  $display ("OR\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000000A;
	  BInput = 32'hF0F0F0F2;
	  //
	  // Test the NOR instruction
	  //
	  #20 OpCode = S_NOR;
	  $display ("XOR\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000000A;
	  BInput = 32'hF001F00A;
	  //
	  // Test the SLL instruction
	  //
	  #20 OpCode = S_SLL;
	  $display ("NOR\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000A00A;
	  BInput = 32'h00000004;
	  //
	  // Test the SRL instruction
	  //
	  #20 OpCode = S_SRL;
	  $display ("SLL\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h0000A00A;
	  BInput = 32'h00000004;
	  //
	  // Test the SRA instruction
	  //
	  #20 OpCode = S_SRA;
	  $display ("SRL\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
				Zero);
	  AInput = 32'h8000A00A;
	  BInput = 32'h00000004;
	  #20 $display ("SRA\t%h %h: %h Ov:%b Z:%b", AInput, BInput, Output, Overflow,
					Zero);
	  #40 $finish;      // Terminate simulation
   end
   
   // Clock generator
   always begin
	  #5 Clock = ~Clock; // Toggle clock every 5 ticks
   end
   
   // Connect DUT to test bench
   ALU32 U_ALU (AInput,
				BInput,
				OpCode,
				Clock,
				Reset,
				Output,
				Overflow,
				Zero);
endmodule