hazard.v

来自「MIPS CPU tested in Icarus Verilog」· Verilog 代码 · 共 104 行

module HazardUnit (Clock, Reset, Instruction, MemWb_WrReg, ExMem_WrReg, DecEx_WrRegRd, DecEx_WrRegRt, DecEx_RegDest, 
		   DecEx_WrRF, ExMem_WrRF, MemWb_WrRF, HazardSelect, FetchDec_Write, PC_Write);

   // ---------------------------- Input ports ----------------------------
   input Clock;
   input Reset;
   input Instruction;
   input MemWb_WrReg;
   input ExMem_WrReg;
   input DecEx_WrRegRd;
   input DecEx_WrRegRt;
   input DecEx_RegDest;
   input DecEx_WrRF;
   input ExMem_WrRF;
   input MemWb_WrRF;

   // ---------------------------- Output ports ----------------------------
   output 	 HazardSelect;
   output 	 FetchDec_Write;
   output 	 PC_Write;

   // Constants
   parameter DataWidth = 32;
   parameter DataWidth2 = 5;

   // ---------------------------- Type of Input ports ----------------------------
   wire Clock;
   wire Reset;
   wire [DataWidth-1:0] Instruction;
   wire [DataWidth2-1:0] MemWb_WrReg;
   wire [DataWidth2-1:0] ExMem_WrReg;
   wire [DataWidth2-1:0] DecEx_WrRegRd;
   wire [DataWidth2-1:0] DecEx_WrRegRt;
   wire [1:0] 		 DecEx_RegDest;
   wire 		 DecEx_WrRF;
   wire 		 ExMem_WrRF;
   wire 		 MemWb_WrRF;

   // ---------------------------- Type of Output ports ----------------------------
   reg 			 HazardSelect;
   reg 			 FetchDecode_Write;
   reg 			 PC_Write;

   always @ (posedge Clock)
     begin
	if (Reset == 1'b1)
	  begin
	     HazardSelect = 1'b0;
	     FetchDecode_Write = 1'b0;
	     PC_Write = 1'b0;
	  end
	else
	  begin
	     if ((DecEx_WrRF == 1'b1) && (DecEx_RegDest == 2'b01))
	       begin
		  if((DecEx_WrRegRd == Instruction[25:21]) || (DecEx_WrRegRd == Instruction[20:16]))
		    begin
		       HazardSelect = 1'b0;
		       FetchDecode_Write = 1'b1;
		       PC_Write = 1'b1;
		    end
		  else
		    begin
		       HazardSelect = 1'b0;
		       FetchDecode_Write = 1'b0;
		       PC_Write = 1'b0;
		    end // else: !if((DecEx_WrRegRd == Instruction[25:21]))
	       end // if ((DecEx_WrRF == 1'b1) && (DecEx_RegDest == 2'b01))
	     else if ((DecEx_WrRF == 1'b1) && (DecEx_RegDest == 2'b00))
	       begin
		  if (DecEx_WrRegRt == Instruction[20:16])
		    begin
		       HazardSelect = 1'b0;
		       FetchDecode_Write = 1'b1;
		       PC_Write = 1'b1;
		    end
		  else
		    begin
		       HazardSelect = 1'b0;
		       FetchDecode_Write = 1'b0;
		       PC_Write = 1'b0;
		    end // else: !if((DecEx_WrRegRt == Instruction[25:21]) || (DecEx_WrRegRt == Instruction[20:16]))
	       end // if ((DecEx_WrRF == 1'b1) && (DecEx_RegDest == 2'b00))
	     else if (((ExMem_WrReg == Instruction[25:21]) || (ExMem_WrReg == Instruction[20:16])) && (ExMem_WrRF == 1'b1))
	       begin
		  HazardSelect = 1'b0;
		  FetchDecode_Write = 1'b1;
		  PC_Write = 1'b1;
	       end
	     else if (((MemWb_WrReg == Instruction[25:21]) || (MemWb_WrReg == Instruction[20:16])) && (MemWb_WrRF == 1'b1))
	       begin
		  HazardSelect = 1'b0;
		  FetchDecode_Write = 1'b1;
		  PC_Write = 1'b1;
	       end
	     else
	       begin
		  HazardSelect = 1'b0;
		  FetchDecode_Write = 1'b0;
		  PC_Write = 1'b0;
	       end // else: !if(((MemWb_WrReg == Instruction[25:21]) || (MemWb_WrReg == Instruction[20:16])) && (MemWb_WrRF == 1'b1))
	  end // else: !if(Reset == 1'b1)
     end // always @ (posedge Clock)
endmodule // HazardUnit