processor.v

MIPS CPU tested in Icarus Verilog

//--------------------------------------------------------------------------------
// Design Name: Processor
// File Name:   processor.v
// Function: The following program implements a MIPS Processor with no forwarding.
// Date: Nov 16th, 2007
//---------------------------------------------------------------------------------

// Include each processor file
`include "alu.v" // File "alu.v" is the 32 bit ALU
`include "fpu.v" // File "fpu.v" is the 32 bit FPU
`include "decoder.v" // File "decoder.v" is the Control Unit
`include "muxes.v" // File "muxes.v" contains the N-bit muxes 2-1, 3-1, and 5-1
`include "adder.v" // File "adder.v" contains the N-bit input adder
`include "signExtension.v" // File "signExtension.v" contains the extension of 16 and 24 sign bits
`include "zeroExtension.v" // File "zeroExtension.v" contains the extension of 16 and 24 zero bits
`include "leftShift.v" // File "leftShift.v" shifts a number 2 bits
`include "PC.v" // File "PC.v" is the program counter
`include "hazard.v"
`include "forward.v"
`include "cache.v"
`include "regfile.v"
//`include "Operations.v" // File "Operations.v" contains all operation codes
//`include "OperationsFP.v" // File "OperationsFP.v" contains some Floating Point operation codes

module processor(DataBusRead,
		 InstructionBusRead,
		 FastClock,
		 SlowClock,
		 Reset,
		 AddressBusData,
		 AddressBusInstruction,
		 DataBusWrite,
		 MemoryRead,
		 MemoryWrite);
   
   // ---------------------------- Input ports ----------------------------
   input DataBusRead;
   input InstructionBusRead;
   input FastClock;
   input SlowClock;
   input Reset;

   // ---------------------------- Output ports ----------------------------
   output AddressBusData;
   output AddressBusInstruction;
   output DataBusWrite;
   output MemoryRead;
   output MemoryWrite;

   // Constants
   parameter 		  DataWidth = 32; // Data width of the memories
   parameter 		  AddressWidth = 10; // Number of bits required to encode address
//   parameter 		  NumElements = 1024; // Number of entries in the memory

   // ---------------------------- Type of Input ports ----------------------------
   wire [DataWidth-1:0] DataBusRead;
   wire [DataWidth-1:0] InstructionBusRead;
   wire 		FastClock;
   wire 		SlowClock;
   wire 		Reset;

   // ---------------------------- Type of Output ports ----------------------------
   wire [AddressWidth-1:0] AddressBusData;
   wire [AddressWidth-1:0] AddressBusInstruction;
   wire [DataWidth-1:0] 	  DataBusWrite;
   wire 			  MemoryRead;
   wire 			  MemoryWrite;

   //-----------------Pipeline Register Declarations-------------------
   reg [57:0] 		  FetchDecode;     //[31:0] RDData
                                           //[57:32] Res(Sum1)
   reg [154:0] 		  DecodeExecute;   //[4:0] fd
                                           //[9:5] Rd
                                           //[14:10] Rt
                                           //[46:15] Ext-32
                                           //[78:47] DataB
                                           //[110:79] DataA
                                           //[136:111] Res(Sum2)
                                           //[137] Src2
                                           //[143:138] ALUOP
                                           //[145:144] RegDest
                                           //[146] Branch
                                           //[147] IntFP
                                           //[148] ArSh
                                           //[149] MemoryWrite
                                           //[150] MemoryRead
                                           //[153:151] Mem2Reg
                                           //[154] Write_RF
   reg [74:0] 		  ExecuteMemory;   //[4:0] RegDestMux
                                           //[36:5] DataB
                                           //[68:37]ResALU/FPU
                                           //[69] Memory_Write
                                           //[70] Memory_Read
                                           //[73:71] Mem2Reg
                                           //[74] Write_RF
   reg [72:0] 		  MemoryWriteBack; //[4:0] RegDestMux
                                           //[36:5] ResALU/FPU
                                           //[68:37] RDData
                                           //[71:69] Mem2Reg
                                           //[72] Write_RF

//   reg []
//   reg [25:0] 		  PC;
   
//#########################################################################################################################//##################################################Internal stage cabling#################################################
//#########################################################################################################################

   //-----------------Fetch Stage-------------------
   wire [25:0] 		  In0_Jump_Out_Branch_Mux; //the connection from OutBranchMux
   wire [25:0] 		  In1JumpMux; //the connection from the JumpTargetAddress
   wire 		  JumpSel; //Selector cable in the jump mux
   wire [25:0] 		  OutJumpMux; //Resulting connection from the selected line in the jump mux
   wire [25:0]		  In0Sum1; //Value of 1 that will be added to In0Sum1 (PC). Assuming the memory is 32 bits wide
   wire [25:0] 		  In1Sum1_PC; //PC entering Sum1 module
   wire [25:0] 		  In0_Branch_Mux_Out_Sum1; //the connection from OutSum1
   wire [25:0] 		  In1BranchMux; //the connection from OutSum2
   wire 		  BranchSel;

   //-----------------Decode Stage-------------------
   wire [31:0] 		  Instruction; //RDData
   wire 		  BranchS; //Branch control signal
   wire 		  Wr_RF; //Write_RF control signal
   wire 		  Src; //Src2 control signal
   wire [5:0] 		  Aluop; //ALUOP control signals
   wire [1:0] 		  Regdest; //RegDest control signals
   wire 		  Memread; //Memory_Read control signal
   wire 		  Memwrite; //Memory_Write control signal
   wire [2:0] 		  Mem2reg; //Mem2Reg control signals
   wire 		  Intfp; //IntFP control signal
   wire 		  Arsh; //ArSh control signal
   wire [25:0] 		  In0Sum2; //Output of Sum1 (PC+1), stored in FetchDecode register
   wire [25:0] 		  In1Sum2; //Immediate shifted by 2 bits
   wire [25:0] 		  OutSum2; //Output from second adder: PC+1+offset
   wire 		  write_rf; 		  
   wire [4:0] 		  OutSrcAMux; //Address of register A (SrcA)
   wire [31:0] 		  OutM2RMuxInWrData; //Write Data into registers
   wire [4:0] 		  OutRegDestMuxWB; //Address of where the data will be stored (register file)
   wire [31:0] 		  DataA; //Data in Address SrcA
   wire [31:0] 		  DataB; //Data in Address SrcB
   wire [31:0] 		  Immed_Ext_32; //Extension to 32 bits of Immediate value
   wire 		  hazardSel;
   wire [1:0]		  fw1Sel;
   wire [1:0]		  fw2Sel;
   wire [17:0] 		  Signals;
   wire 		  fdWr;
   wire 		  PC;

   //-----------------Execute Stage-------------------
   wire [3:0] 		  WBSignals;
   wire [1:0] 		  MSignals;
   wire 		  Branch_Sig;
   wire [1:0] 		  RegDest_Sig;
   wire [5:0] 		  ALUOP_Sig;
   wire 		  Src2_Sig;
   wire 		  IntFP_Sig;
   wire [31:0] 		  dataA;
   wire [31:0] 		  dataB_OutAluMux;
   wire 		  Overflow;
   wire 		  Zero;
   wire [31:0] 		  ALURes;
   wire [31:0] 		  FPURes;
   wire [31:0] 		  ALU_FPU_Out;
   wire [31:0] 		  In0AluMux;
   wire [31:0] 		  In1AluMux;
   wire [4:0] 		  In0DestMux;
   wire [4:0] 		  In1DestMux;
   wire [4:0] 		  In2DestMux;
   wire [4:0] 		  OutDestMux;

   //-----------------Memory Stage-------------------
   wire [3:0] 		  WbSignals;
   wire 		  mem_read;
   wire 		  mem_write;
   wire [31:0] 		  memdataAddress;
   wire [31:0] 		  memdataWrData;
   wire [31:0] 		  memdataRdData;
   wire [4:0] 		  reg_Dest;

   //-----------------Write Back Stage-------------------
   wire [2:0]		  memtoreg;
   wire [31:0]		  memRdData; // = In5Mem2RegMux
   wire [31:0] 		  zero16; // = In4Mem2RegMux
   wire [31:0] 		  sign16; // = In3Mem2RegMux
   wire [31:0] 		  zero24; // = In2Mem2RegMux
   wire [31:0] 		  sign24; // = In1Mem2RegMux
   wire [31:0] 		  ALU_FPU_Res; // = In0Mem2RegMux

//#########################################################################################################################//##################################################Modules Initialization#################################################
//#########################################################################################################################


   //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!Fetch Modules!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
   assign 		  In1JumpMux = FetchDecode[25:0];
//   always PC = OutJumpMux;
//   assign AddressBusInstruction = PC[AddressWidth-1:0];
//   assign In1Sum1_PC = PC;
   //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Adder (PC+1);;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   assign 		  In0Sum1 = 26'b1;
   adder Adder1 (.AInput(In0Sum1),
		 .BInput(In1Sum1_PC),
		 .Output(In0_Branch_Mux_Out_Sum1));

   //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Branch Mux;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   MUX_2_1 #26 BranchMux (.AInput(In0_Branch_Mux_Out_Sum1),
			  .BInput(In1BranchMux),
			  .Select(BranchSel),
			  .Output(In0_Jump_Out_Branch_Mux));
   
   //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Jump Mux;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   MUX_2_1 #26 JumpMux (.AInput(In0_Jump_Out_Branch_Mux),
			.BInput(In1JumpMux),
			.Select(JumpSel),
			.Output(OutJumpMux));

   //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;PC;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   PC pc (.AInput(OutJumpMux),
	  .Clock(SlowClock),
	  .Reset(Reset),
	  .Output(In1Sum1_PC));
   assign 		  AddressBusInstruction = In1Sum1_PC[AddressWidth-1:0];

//   delay #26 d (.AInput(In1Sum1_PC),
//		.Output(In1Sum1_PC));

   assign 		  Instruction = FetchDecode[31:0];

   //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Instruction Memory;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   //%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Instruction Memory needs instantiation%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
   //The input to the memory is AddressBusInstruction
   //The output of the memory and input to the CPU is InstructionBusRead

   //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!Decode Modules!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
   //HazardUnit hazard(.Clock(FastClock),
//		     .Reset(Reset),
//		     .Instruction(FetchDecode[31:0]),
//		     .RegDest(DecodeExecute[145:144]),
//		     .DecEx_WrRegT(DecodeExecute[14:0]),
//		     .DecEx_WrRF(DecodeExecute[154]),
//		     .ExMem_WrReg(ExecuteMemory[4:0]),
//		     .ExMem_WrRF(ExecuteMemory[74]),
//		     .MemWb_WrReg(MemoryWriteBack[4:0]),
//		     .MemWb_WrRF(MemoryWriteBack[72]),
		     //.DecEx_RegDest(DecodeExecute[145:144]),
		     //.DecEx_WrRF(DecodeExecute[154]),
		     //.DecEx_WrReg1(DecodeExecute[14:10]),
		     //.DecEx_WrReg2(DecodeExecute[9:5]),
		     //.ExMem_WrRF(ExecuteMemory[74]),
		     //.ExMem_WrReg(ExecuteMemory[4:0]),
		     //.MemWb_WrRF(MemoryWriteBack[72]),
		     //.MemWb_WrReg(MemoryWriteBack[4:0]),
		    // .PC_Write(hazardPCWr),
		    // .FetchDec_Write(hazardFetchDecWr),
//		     .HazardSelect(hazardSel),
//		     .Forward1(fw1Sel),
//		     .Forward2(fw2Sel));
   
   //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Control Unit;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   decoder Decoder (.Clock(FastClock),
		    .Reset(Reset),
		    .Instruction(FetchDecode[31:0]),
		    .Branch(BranchS),
		    .Jump(JumpSel),
		    .Write_RF(Wr_RF),