processor_tb.v

MIPS CPU tested in Icarus Verilog

//----------------------------------------------------------------------------
//
// File Name:   processor_tb.v
//
// Type:        Test bench
//
// Description: This is the test bench for the 32-bit processor module. The
//              test bench excercises the following instructions:
//
//                 ADD, ADDI, ADDU, ADDIU, SUB, SUBU, MULT, MULTU, DIV, DIVU,
//                 AND, ANDI, OR, ORI, XOR, XORI, NOR, SLL, SLLV, SRL, SRLV,
//                 SRA, SRAV, BEQ, BNE, J, LB, LBU, LH, LW, SB, SH, SW
//
// Author:      Abelardo L髉ez Lagunas
//
//----------------------------------------------------------------------------
// Release history
//
// Version  Date      Description  
//   1.0    02/11/06  File created
//   1.1    14/11/06  Load program into instruction memory
//----------------------------------------------------------------------------
//
// Keywords: Processor test bench
//
//----------------------------------------------------------------------------
//
// Include the design under test below
`include "processor.v"
//
// Test bench code starts here
//
module processor_tb();
   //
   // Declare the global parameters
   //
   parameter DataWidth = 32;     // Data width of the memories
   parameter AddressWidth = 10;  // Number of bits required to encode address
   parameter NumElements = 1024; // Number of entries in the memory
   //
   // Declare the external memories, both are the same size and width
   //
   reg [DataWidth-1:0] DataMemory [0:NumElements-1];
   reg [DataWidth-1:0] InstructionMemory [0:NumElements-1];
   //
   // Declare the inputs of the module under test as registers and the outputs
   // as wires
   //
   reg [DataWidth-1:0] DataBusRead;
   reg [DataWidth-1:0] InstructionBusRead;
   reg                 FastClock;
   reg                 SlowClock;
   reg                 Reset;
   wire [AddressWidth-1:0] AddressBusData;
   wire [AddressWidth-1:0] AddressBusInstruction;
   wire [DataWidth-1:0]    DataBusWrite;
   wire                    MemoryRead;
   wire                    MemoryWrite;
   //
   // Use an integer varible to zero out memory contents
   //
   integer                 i;
   //
   // Include the definition of all the processor operations
   //
`include "Operations.v"
`include "OperationsFP.v"
   //
   // Initialize all variables
   //
   initial begin
	  $dumpfile ("processor.vcd");
	  // For now, dump all variables of the design
	  $dumpvars;
	  	  	  
	  SlowClock = 1'b1;        // Initial value of clocks
	  FastClock = 1'b1;
	  Reset = 1'b1;
	  //
	  // Clear the data memory
	  //
	  for (i = 0; i < NumElements; i = i + 1)
        DataMemory[i] = 0;
	  //
	  // Now load a simple program into the instruction memory
	  //
	  $readmemb("program.s", InstructionMemory);
	  #10 Reset = 1'b0;	  

	  #1000 $finish;      // Terminate simulation
   end
   //
   // Clock generators
   //
   always
	 begin
		#2 FastClock = ~FastClock;
	 end
   
   always @ (posedge FastClock) 
	 begin
		#10 SlowClock = ~SlowClock; // Toggle clock every 5 ticks
	 end
   //
   // For simplicity assume that the memory responds faster than a pipeline
   // stage
   //
   always @ (posedge FastClock)
	 begin
		InstructionBusRead = InstructionMemory[AddressBusInstruction];
		if (MemoryRead == 1'b1 && MemoryWrite == 1'b0)
		  DataBusRead = DataMemory[AddressBusData];
		else
		  if (MemoryRead == 1'b0 && MemoryWrite == 1'b1)
			DataMemory[AddressBusData] = DataBusWrite;
		  else
			DataBusRead = 32'hZZZZZZZZ;
	 end // always @ (posedge FastClock)
   
   // Connect DUT to test bench

   processor MIPS(DataBusRead,
                  InstructionBusRead,
                  FastClock,
                  SlowClock,
                  Reset,
                  AddressBusData,
                  AddressBusInstruction,
                  DataBusWrite,
                  MemoryRead,
                  MemoryWrite);
endmodule