regfile.v

MIPS CPU tested in Icarus Verilog

//--------------------------------------------------------------------------
// FILE NAME      : regfile.v
// TYPE           : behavioral model
//
// DESCRIPTION    : This module implements a three-ported register file. Two
//                  read ports and one write port. All ports have the same
//                  clock domain. Data is read and written to the register
//                  on the rising edge of the clock.
//
// AUTHOR         : Abelardo Lopez-Lagunas
//
//--------------------------------------------------------------------------
// Release History
// VERSION  Date      AUTHOR             DESCRIPTION
//   1.0    26/09/05  Abelardo Lopez     File created
//--------------------------------------------------------------------------
// KEYWORDS  : Register File
//--------------------------------------------------------------------------
// PURPOSE   : This is the behavioral model of a simple register file
//--------------------------------------------------------------------------
// PARAMETERS
//    NAME           RANGE       DEFAULT         DESCRIPTION
// NumElements       1-N           32    Entries in the register file
// AddressBits       1-log2(N)      5    Required bits to encode # of entries
// DataWidth         1-M           32    Width of each entry (in bits)
//--------------------------------------------------------------------------

// Implement a generic register file. Two read ports and one write port
module RegisterFile(Resetb,
                    Clock,
                    ReadAddressA,
		    ReadDataA,		   
		    ReadAddressB,
		    ReadDataB,				
		    WriteAddress,
                    WriteData,
		    Write);
   
   parameter NumElements = 32;  // Number of entries in the RF
   parameter AddressBits = 5;   // Number of bits required to encode address
   parameter DataWidth = 32;    // Data width of the register file
   
   // Port definitions
   input     Resetb;
   input     Clock;
   input [AddressBits-1:0] ReadAddressA;
   input [AddressBits-1:0] ReadAddressB;
   input [AddressBits-1:0] WriteAddress;   
   input [DataWidth-1:0]   WriteData;
   input 				   Write; 				   
   output [DataWidth-1:0]  ReadDataA;
   output [DataWidth-1:0]  ReadDataB;
   
   // Allocate the register file space and the output registers
   reg [DataWidth-1:0] 	   RFMemory [0:NumElements-1];
   reg [DataWidth-1:0] 	   ReadDataA;
   reg [DataWidth-1:0] 	   ReadDataB;
   
   // Integer variable for the initialization loop
   integer                 j;

   // Initialize the register file. The circuit is synchronous and thus
   // the reset is checked on the positive edge of the clock 
   always @(posedge Clock)
     begin
        if (Resetb == 1'b1)       // Reset conditon, clear all the registers
          begin
			 ReadDataA <= 0;      // Clear output registers
			 ReadDataB <= 0;      // Zero-out the register file
			 for (j = 0; j < NumElements; j = j + 1)
               RFMemory[j] <= 0;
          end
        else
		  // On each cycle all three ports are accessed
		  begin                        // Normal operation
			 if (Write == 1'b1)        // Update the register file
			   begin
				  RFMemory[WriteAddress] <= WriteData;
				  ReadDataA <= RFMemory[ReadAddressA]; // Always read
				  ReadDataB <= RFMemory[ReadAddressB]; // two ports
			   end
			 else				       // Always read both ports per cycle
			   begin
				  ReadDataA <= RFMemory[ReadAddressA];
				  ReadDataB <= RFMemory[ReadAddressB];			 
			   end
		  end // else: !if(Resetb == 1'b0)
	 end // always @ (posedge Clock)   
endmodule // RegisterFile