counter.tan.rpt

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· RPT 代码 · 共 242 行 · 第 1/2 页

; Slack ; Required tsu ; Actual tsu ; From ; To     ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A   ; None         ; 11.000 ns  ; EN   ; C~reg0 ; PULSE    ;
+-------+--------------+------------+------+--------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 15.000 ns  ; COUNT[3]~reg0 ; COUNT[3] ; EN         ;
; N/A   ; None         ; 15.000 ns  ; COUNT[2]~reg0 ; COUNT[2] ; EN         ;
; N/A   ; None         ; 15.000 ns  ; COUNT[1]~reg0 ; COUNT[1] ; EN         ;
; N/A   ; None         ; 15.000 ns  ; COUNT[0]~reg0 ; COUNT[0] ; EN         ;
; N/A   ; None         ; 8.000 ns   ; C~reg0        ; C        ; PULSE      ;
+-------+--------------+------------+---------------+----------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -3.000 ns ; EN   ; C~reg0 ; PULSE    ;
+---------------+-------------+-----------+------+--------+----------+


+-------------------------------------------------------------------------------------------+
; Minimum tco                                                                               ;
+---------------+------------------+----------------+---------------+----------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From          ; To       ; From Clock ;
+---------------+------------------+----------------+---------------+----------+------------+
; N/A           ; None             ; 8.000 ns       ; C~reg0        ; C        ; PULSE      ;
; N/A           ; None             ; 15.000 ns      ; COUNT[0]~reg0 ; COUNT[0] ; EN         ;
; N/A           ; None             ; 15.000 ns      ; COUNT[1]~reg0 ; COUNT[1] ; EN         ;
; N/A           ; None             ; 15.000 ns      ; COUNT[2]~reg0 ; COUNT[2] ; EN         ;
; N/A           ; None             ; 15.000 ns      ; COUNT[3]~reg0 ; COUNT[3] ; EN         ;
+---------------+------------------+----------------+---------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jan 01 16:43:30 2008
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counter -c counter
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node EN is an undefined clock
    Info: Assuming node PULSE is an undefined clock
Info: No valid register-to-register paths exist for clock EN
Info: Clock PULSE has Internal fmax of 76.92 MHz between source register cntbuf[0] and destination register C~reg0 (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'cntbuf[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock PULSE to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock PULSE to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'cntbuf[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register C~reg0 (data pin = EN, clock pin = PULSE) is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'EN'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock PULSE to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock EN to destination pin COUNT[3] through register COUNT[3]~reg0 is 15.000 ns
    Info: + Longest clock path from clock EN to source register is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'EN'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC6; Fanout = 1; REG Node = 'COUNT[3]~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 1; REG Node = 'COUNT[3]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'COUNT[3]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register C~reg0 (data pin = EN, clock pin = PULSE) is -3.000 ns
    Info: + Longest clock path from clock PULSE to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'EN'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Minimum tco from clock PULSE to destination pin C through register C~reg0 is 8.000 ns
    Info: + Shortest clock path from clock PULSE to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'C'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jan 01 16:43:30 2008
    Info: Elapsed time: 00:00:00