counter.vhd

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· VHDL 代码 · 共 39 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY counter IS
	PORT
	(EN: IN	STD_LOGIC;
	PULSE: IN	STD_LOGIC;
	COUNT: OUT	STD_LOGIC_VECTOR(3 downto 0);
	C: OUT	STD_LOGIC);--进位
END counter;

architecture arch of counter is
	shared variable cntbuf : STD_LOGIC_VECTOR(3 downto 0);
begin
	add:process(EN,PULSE)
	begin
		if Rising_edge(PULSE) and EN='1' then
			if cntbuf="1001" then
				cntbuf:="0000";
				C<='1';
			else
				cntbuf:=cntbuf+1;
				C<='0';
			end if;
		end if;
		if EN='0' then
			cntbuf:="0000";
		end if;
	end process add;
	
	enFall:process(EN)
	begin
		if Falling_edge(EN) then
			COUNT<=cntbuf;
		end if;
	end process enFall;
end arch;