freqm.hier_info

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· HIER_INFO 代码 · 共 266 行

|freqm
CATSEL[5] <= dispselector:inst.CATSEL[5]
CATSEL[4] <= dispselector:inst.CATSEL[4]
CATSEL[3] <= dispselector:inst.CATSEL[3]
CATSEL[2] <= dispselector:inst.CATSEL[2]
CATSEL[1] <= dispselector:inst.CATSEL[1]
CATSEL[0] <= dispselector:inst.CATSEL[0]
CLK => divider1000:inst2.iCLK
CLK => selector:inst16.MCLK
SIGNAL => selector:inst16.SIG
SWITCH[0] => selector:inst16.SW[0]
SWITCH[1] => selector:inst16.SW[1]
DIGSGN[7] <= dispselector:inst.DIGSGN[7]
DIGSGN[6] <= dispselector:inst.DIGSGN[6]
DIGSGN[5] <= dispselector:inst.DIGSGN[5]
DIGSGN[4] <= dispselector:inst.DIGSGN[4]
DIGSGN[3] <= dispselector:inst.DIGSGN[3]
DIGSGN[2] <= dispselector:inst.DIGSGN[2]
DIGSGN[1] <= dispselector:inst.DIGSGN[1]
DIGSGN[0] <= dispselector:inst.DIGSGN[0]


|freqm|dispselector:inst
CLK => POS[1].CLK
CLK => POS[0].CLK
CLK => POS[2].CLK
NUM1[0] => Mux~8.IN19
NUM1[1] => Mux~6.IN10
NUM1[1] => Mux~7.IN10
NUM1[1] => Mux~8.IN18
NUM1[2] => Mux~6.IN9
NUM1[2] => Mux~7.IN9
NUM1[2] => Mux~8.IN17
NUM1[3] => DGT[3].IN2
NUM1[3] => Mux~6.IN8
NUM1[3] => Mux~7.IN8
NUM1[3] => Mux~8.IN16
NUM2[0] => Mux~11.IN19
NUM2[1] => Mux~9.IN10
NUM2[1] => Mux~10.IN10
NUM2[1] => Mux~11.IN18
NUM2[2] => Mux~9.IN9
NUM2[2] => Mux~10.IN9
NUM2[2] => Mux~11.IN17
NUM2[3] => DGT[3].IN3
NUM2[3] => Mux~9.IN8
NUM2[3] => Mux~10.IN8
NUM2[3] => Mux~11.IN16
NUM3[0] => Mux~14.IN19
NUM3[1] => Mux~12.IN10
NUM3[1] => Mux~13.IN10
NUM3[1] => Mux~14.IN18
NUM3[2] => Mux~12.IN9
NUM3[2] => Mux~13.IN9
NUM3[2] => Mux~14.IN17
NUM3[3] => DGT[3].IN4
NUM3[3] => Mux~12.IN8
NUM3[3] => Mux~13.IN8
NUM3[3] => Mux~14.IN16
NUM4[0] => Mux~17.IN19
NUM4[1] => Mux~15.IN10
NUM4[1] => Mux~16.IN10
NUM4[1] => Mux~17.IN18
NUM4[2] => Mux~15.IN9
NUM4[2] => Mux~16.IN9
NUM4[2] => Mux~17.IN17
NUM4[3] => DGT[3].IN5
NUM4[3] => Mux~15.IN8
NUM4[3] => Mux~16.IN8
NUM4[3] => Mux~17.IN16
NUM5[0] => Mux~20.IN19
NUM5[1] => Mux~18.IN10
NUM5[1] => Mux~19.IN10
NUM5[1] => Mux~20.IN18
NUM5[2] => Mux~18.IN9
NUM5[2] => Mux~19.IN9
NUM5[2] => Mux~20.IN17
NUM5[3] => DGT[3].IN6
NUM5[3] => Mux~18.IN8
NUM5[3] => Mux~19.IN8
NUM5[3] => Mux~20.IN16
NUM6[0] => Mux~23.IN19
NUM6[1] => Mux~21.IN10
NUM6[1] => Mux~22.IN10
NUM6[1] => Mux~23.IN18
NUM6[2] => Mux~21.IN9
NUM6[2] => Mux~22.IN9
NUM6[2] => Mux~23.IN17
NUM6[3] => DGT[3].IN7
NUM6[3] => Mux~21.IN8
NUM6[3] => Mux~22.IN8
NUM6[3] => Mux~23.IN16
DIGSGN[7] <= <GND>
DIGSGN[6] <= Mux~30.DB_MAX_OUTPUT_PORT_TYPE
DIGSGN[5] <= Mux~29.DB_MAX_OUTPUT_PORT_TYPE
DIGSGN[4] <= Mux~28.DB_MAX_OUTPUT_PORT_TYPE
DIGSGN[3] <= Mux~27.DB_MAX_OUTPUT_PORT_TYPE
DIGSGN[2] <= Mux~26.DB_MAX_OUTPUT_PORT_TYPE
DIGSGN[1] <= Mux~25.DB_MAX_OUTPUT_PORT_TYPE
DIGSGN[0] <= Mux~24.DB_MAX_OUTPUT_PORT_TYPE
CATSEL[5] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
CATSEL[4] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
CATSEL[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
CATSEL[2] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
CATSEL[1] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
CATSEL[0] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|freqm|divider1000:inst2
iCLK => counter[7].CLK
iCLK => counter[6].CLK
iCLK => counter[5].CLK
iCLK => counter[4].CLK
iCLK => counter[3].CLK
iCLK => counter[2].CLK
iCLK => counter[1].CLK
iCLK => counter[0].CLK
iCLK => clk_o.CLK
iCLK => counter[8].CLK
oCLK <= clk_o.DB_MAX_OUTPUT_PORT_TYPE


|freqm|counter:inst10
EN => cntbuf~4.OUTPUTSELECT
EN => cntbuf~5.OUTPUTSELECT
EN => cntbuf~6.OUTPUTSELECT
EN => cntbuf~7.OUTPUTSELECT
EN => C~0.OUTPUTSELECT
EN => falling_edge~0.IN0
PULSE => cntbuf[2].CLK
PULSE => cntbuf[1].CLK
PULSE => cntbuf[0].CLK
PULSE => C~reg0.CLK
PULSE => cntbuf[3].CLK
COUNT[0] <= COUNT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C <= C~reg0.DB_MAX_OUTPUT_PORT_TYPE


|freqm|selector:inst16
MCLK => Pulse~0.DATAB
HCLK => En~2.DATAA
SIG => En~2.DATAB
SIG => Pulse~0.DATAA
SIG => SIG2.CLK
En <= En~3.DB_MAX_OUTPUT_PORT_TYPE
Pulse <= Pulse~0.DB_MAX_OUTPUT_PORT_TYPE
SW[0] => En~0.IN0
SW[0] => Pulse~0.OUTPUTSELECT
SW[1] => En~1.IN0
SW[1] => reduce_nor~1.IN0


|freqm|divider2:inst1
iCLK => counter[8].CLK
iCLK => counter[7].CLK
iCLK => counter[6].CLK
iCLK => counter[5].CLK
iCLK => counter[4].CLK
iCLK => counter[3].CLK
iCLK => counter[2].CLK
iCLK => counter[1].CLK
iCLK => counter[0].CLK
iCLK => oCLK~reg0.CLK
iCLK => counter[9].CLK
oCLK <= oCLK~reg0.DB_MAX_OUTPUT_PORT_TYPE


|freqm|counter:inst11
EN => cntbuf~4.OUTPUTSELECT
EN => cntbuf~5.OUTPUTSELECT
EN => cntbuf~6.OUTPUTSELECT
EN => cntbuf~7.OUTPUTSELECT
EN => C~0.OUTPUTSELECT
EN => falling_edge~0.IN0
PULSE => cntbuf[2].CLK
PULSE => cntbuf[1].CLK
PULSE => cntbuf[0].CLK
PULSE => C~reg0.CLK
PULSE => cntbuf[3].CLK
COUNT[0] <= COUNT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C <= C~reg0.DB_MAX_OUTPUT_PORT_TYPE


|freqm|counter:inst12
EN => cntbuf~4.OUTPUTSELECT
EN => cntbuf~5.OUTPUTSELECT
EN => cntbuf~6.OUTPUTSELECT
EN => cntbuf~7.OUTPUTSELECT
EN => C~0.OUTPUTSELECT
EN => falling_edge~0.IN0
PULSE => cntbuf[2].CLK
PULSE => cntbuf[1].CLK
PULSE => cntbuf[0].CLK
PULSE => C~reg0.CLK
PULSE => cntbuf[3].CLK
COUNT[0] <= COUNT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C <= C~reg0.DB_MAX_OUTPUT_PORT_TYPE


|freqm|counter:inst13
EN => cntbuf~4.OUTPUTSELECT
EN => cntbuf~5.OUTPUTSELECT
EN => cntbuf~6.OUTPUTSELECT
EN => cntbuf~7.OUTPUTSELECT
EN => C~0.OUTPUTSELECT
EN => falling_edge~0.IN0
PULSE => cntbuf[2].CLK
PULSE => cntbuf[1].CLK
PULSE => cntbuf[0].CLK
PULSE => C~reg0.CLK
PULSE => cntbuf[3].CLK
COUNT[0] <= COUNT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C <= C~reg0.DB_MAX_OUTPUT_PORT_TYPE


|freqm|counter:inst14
EN => cntbuf~4.OUTPUTSELECT
EN => cntbuf~5.OUTPUTSELECT
EN => cntbuf~6.OUTPUTSELECT
EN => cntbuf~7.OUTPUTSELECT
EN => C~0.OUTPUTSELECT
EN => falling_edge~0.IN0
PULSE => cntbuf[2].CLK
PULSE => cntbuf[1].CLK
PULSE => cntbuf[0].CLK
PULSE => C~reg0.CLK
PULSE => cntbuf[3].CLK
COUNT[0] <= COUNT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C <= C~reg0.DB_MAX_OUTPUT_PORT_TYPE


|freqm|counter:inst15
EN => cntbuf~4.OUTPUTSELECT
EN => cntbuf~5.OUTPUTSELECT
EN => cntbuf~6.OUTPUTSELECT
EN => cntbuf~7.OUTPUTSELECT
EN => C~0.OUTPUTSELECT
EN => falling_edge~0.IN0
PULSE => cntbuf[2].CLK
PULSE => cntbuf[1].CLK
PULSE => cntbuf[0].CLK
PULSE => C~reg0.CLK
PULSE => cntbuf[3].CLK
COUNT[0] <= COUNT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C <= C~reg0.DB_MAX_OUTPUT_PORT_TYPE