freqm.map.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 22 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 01 14:16:19 2008 " "Info: Processing started: Tue Jan 01 14:16:19 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off freqm -c freqm " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off freqm -c freqm" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freqm.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file freqm.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 freqm " "Info: Found entity 1: freqm" {  } { { "D:/051750/freqm/freqm.bdf" "freqm" "" { Schematic "D:/051750/freqm/freqm.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divider2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divider2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divider2-arch " "Info: Found design unit 1: divider2-arch" {  } { { "D:/051750/freqm/divider2.vhd" "divider2-arch" "" { Text "D:/051750/freqm/divider2.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 divider2 " "Info: Found entity 1: divider2" {  } { { "D:/051750/freqm/divider2.vhd" "divider2" "" { Text "D:/051750/freqm/divider2.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "dispselector.vhd 2 1 " "Info: Using design file dispselector.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dispselector-arch " "Info: Found design unit 1: dispselector-arch" {  } { { "D:/051750/freqm/dispselector.vhd" "dispselector-arch" "" { Text "D:/051750/freqm/dispselector.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dispselector " "Info: Found entity 1: dispselector" {  } { { "D:/051750/freqm/dispselector.vhd" "dispselector" "" { Text "D:/051750/freqm/dispselector.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "divider1000.vhd 2 1 " "Info: Using design file divider1000.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divider1000-arch " "Info: Found design unit 1: divider1000-arch" {  } { { "D:/051750/freqm/divider1000.vhd" "divider1000-arch" "" { Text "D:/051750/freqm/divider1000.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 divider1000 " "Info: Found entity 1: divider1000" {  } { { "D:/051750/freqm/divider1000.vhd" "divider1000" "" { Text "D:/051750/freqm/divider1000.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "counter.vhd 2 1 " "Info: Using design file counter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-arch " "Info: Found design unit 1: counter-arch" {  } { { "D:/051750/freqm/counter.vhd" "counter-arch" "" { Text "D:/051750/freqm/counter.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "D:/051750/freqm/counter.vhd" "counter" "" { Text "D:/051750/freqm/counter.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "selector.vhd 2 1 " "Info: Using design file selector.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 selector-arch " "Info: Found design unit 1: selector-arch" {  } { { "D:/051750/freqm/selector.vhd" "selector-arch" "" { Text "D:/051750/freqm/selector.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 selector " "Info: Found entity 1: selector" {  } { { "D:/051750/freqm/selector.vhd" "selector" "" { Text "D:/051750/freqm/selector.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "divider2:inst1\|counter\[0\]~10 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: divider2:inst1\|counter\[0\]~10" {  } { { "D:/051750/freqm/divider2.vhd" "" "counter\[0\]~10" { Text "D:/051750/freqm/divider2.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "d:/program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "d:/program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "d:/program files/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "d:/program files/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/altera/quartus41/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "d:/program files/altera/quartus41/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "d:/program files/altera/quartus41/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "d:/program files/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "d:/program files/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/altera/quartus41/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "d:/program files/altera/quartus41/libraries/megafunctions/look_add.tdf" "look_add" "" { Text "d:/program files/altera/quartus41/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../program files/altera/quartus41/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "d:/program files/altera/quartus41/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "d:/program files/altera/quartus41/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "8 " "Info: Ignored 8 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "8 " "Info: Ignored 8 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "DIGSGN\[7\] GND " "Warning: Pin DIGSGN\[7\] stuck at GND" {  } { { "D:/051750/freqm/freqm.bdf" "" "" { Schematic "D:/051750/freqm/freqm.bdf" { { 216 1016 1192 232 "DIGSGN\[0..7\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin CLK to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "145 " "Info: Implemented 145 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "122 " "Info: Implemented 122 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "5 " "Info: Implemented 5 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 01 14:16:24 2008 " "Info: Processing ended: Tue Jan 01 14:16:24 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}