freqm.map.rpt

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· RPT 代码 · 共 249 行 · 第 1/2 页

+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                     ;
+-----------------------------------+------------+------+-------------------------------------------------+
; Compilation Hierarchy Node        ; Macrocells ; Pins ; Full Hierarchy Name                             ;
+-----------------------------------+------------+------+-------------------------------------------------+
; |freqm                            ; 122        ; 18   ; |freqm                                          ;
;    |counter:inst10|               ; 10         ; 0    ; |freqm|counter:inst10                           ;
;    |counter:inst11|               ; 10         ; 0    ; |freqm|counter:inst11                           ;
;    |counter:inst12|               ; 10         ; 0    ; |freqm|counter:inst12                           ;
;    |counter:inst13|               ; 10         ; 0    ; |freqm|counter:inst13                           ;
;    |counter:inst14|               ; 10         ; 0    ; |freqm|counter:inst14                           ;
;    |counter:inst15|               ; 8          ; 0    ; |freqm|counter:inst15                           ;
;    |dispselector:inst|            ; 41         ; 0    ; |freqm|dispselector:inst                        ;
;    |divider1000:inst2|            ; 10         ; 0    ; |freqm|divider1000:inst2                        ;
;    |divider2:inst1|               ; 11         ; 0    ; |freqm|divider2:inst1                           ;
;       |lpm_counter:counter_rtl_0| ; 10         ; 0    ; |freqm|divider2:inst1|lpm_counter:counter_rtl_0 ;
;    |selector:inst16|              ; 1          ; 0    ; |freqm|selector:inst16                          ;
+-----------------------------------+------------+------+-------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/051750/freqm/freqm.map.eqn.


+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                       ;
+----------------------------------------------------------------------------+-----------------+
; File Name                                                                  ; Used in Netlist ;
+----------------------------------------------------------------------------+-----------------+
; freqm.bdf                                                                  ; yes             ;
; divider2.vhd                                                               ; yes             ;
; D:/051750/freqm/dispselector.vhd                                           ; yes             ;
; D:/051750/freqm/divider1000.vhd                                            ; yes             ;
; D:/051750/freqm/counter.vhd                                                ; yes             ;
; D:/051750/freqm/selector.vhd                                               ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf  ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/addcore.inc      ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/look_add.inc     ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/addcore.tdf      ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf  ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/look_add.tdf     ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/altshift.tdf     ; yes             ;
+----------------------------------------------------------------------------+-----------------+


+-----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary   ;
+----------------------+------------------------+
; Resource             ; Usage                  ;
+----------------------+------------------------+
; Logic cells          ; 122                    ;
; Total registers      ; 78                     ;
; I/O pins             ; 18                     ;
; Shareable expanders  ; 5                      ;
; Parallel expanders   ; 16                     ;
; Maximum fan-out node ; selector:inst16|En~193 ;
; Maximum fan-out      ; 48                     ;
; Total fan-out        ; 784                    ;
; Average fan-out      ; 5.41                   ;
+----------------------+------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jan 01 14:16:19 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off freqm -c freqm
Info: Found 1 design units, including 1 entities, in source file freqm.bdf
    Info: Found entity 1: freqm
Info: Found 2 design units, including 1 entities, in source file divider2.vhd
    Info: Found design unit 1: divider2-arch
    Info: Found entity 1: divider2
Info: Using design file dispselector.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: dispselector-arch
    Info: Found entity 1: dispselector
Info: Using design file divider1000.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: divider1000-arch
    Info: Found entity 1: divider1000
Info: Using design file counter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter-arch
    Info: Found entity 1: counter
Info: Using design file selector.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: selector-arch
    Info: Found entity 1: selector
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: divider2:inst1|counter[0]~10
Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../../program files/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 8 buffer(s)
    Info: Ignored 8 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin DIGSGN[7] stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin CLK to global clock signal
Info: Implemented 145 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 14 output pins
    Info: Implemented 122 macrocells
    Info: Implemented 5 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Jan 01 14:16:24 2008
    Info: Elapsed time: 00:00:05