selector.vhd

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· VHDL 代码 · 共 33 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY selector IS
	PORT(MCLK:in std_logic;
		--KCLK:in std_logic;
		HCLK:in std_logic;
		SIG:in std_logic;
		En:out std_logic;
		Pulse:out std_logic;
		SW:in std_logic_vector(1 downto 0));--SW(0):频率/周期  SW(1):周期/脉宽
END selector;

ARCHITECTURE arch OF selector IS
	SIGNAL SIG2 : STD_LOGIC;
BEGIN

	En<=SIG2 when(SW="01") else--周期
	SIG when(SW="11") else--脉宽
	HCLK;--频率

	Pulse<=MCLK when(SW(0)='1') else--周期/脉宽
	SIG;--频率

	sigdiv:PROCESS(SIG)--信号二分频
	BEGIN
		if Rising_edge(SIG) then
			SIG2<=not SIG2;
		end if;
	END PROCESS sigdiv;

END arch;