freqm.tan.summary

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -3.000 ns
From           : SWITCH[0]
To             : counter:inst10|C
From Clock     : 
To Clock       : SWITCH[0]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 55.000 ns
From           : counter:inst14|COUNT[3]
To             : DIGSGN[0]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 48.000 ns
From           : SIGNAL
To             : counter:inst14|C
From Clock     : 
To Clock       : SWITCH[0]
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 26.000 ns
From           : dispselector:inst|POS[1]
To             : CATSEL[2]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'SWITCH[0]'
Slack          : N/A
Required Time  : None
Actual Time    : 17.24 MHz ( period = 58.000 ns )
From           : counter:inst15|cntbuf[0]
To             : counter:inst15|COUNT[0]
From Clock     : SWITCH[0]
To Clock       : SWITCH[0]
Failed Paths   : 0

Type           : Clock Setup: 'SIGNAL'
Slack          : N/A
Required Time  : None
Actual Time    : 17.24 MHz ( period = 58.000 ns )
From           : counter:inst15|cntbuf[0]
To             : counter:inst15|COUNT[0]
From Clock     : SIGNAL
To Clock       : SIGNAL
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 21.28 MHz ( period = 47.000 ns )
From           : counter:inst15|cntbuf[0]
To             : counter:inst15|COUNT[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Hold: 'SIGNAL'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : selector:inst16|SIG2
To             : counter:inst14|C
From Clock     : SIGNAL
To Clock       : SIGNAL
Failed Paths   : 9

Type           : Clock Hold: 'CLK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : divider2:inst1|oCLK
To             : counter:inst14|C
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 9

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 18

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