divider.tan.summary

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.000 ns
From           : clk_o
To             : oCLK
From Clock     : iCLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.000 ns
From           : clk_o
To             : oCLK
From Clock     : iCLK
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'iCLK'
Slack          : N/A
Required Time  : None
Actual Time    : 76.92 MHz ( period = 13.000 ns )
From           : counter[0]
To             : counter[0]
From Clock     : iCLK
To Clock       : iCLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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