dispselector.map.qmsg

以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 01 17:02:32 2008 " "Info: Processing started: Tue Jan 01 17:02:32 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off dispselector -c dispselector " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off dispselector -c dispselector" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dispselector.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dispselector.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dispselector-arch " "Info: Found design unit 1: dispselector-arch" {  } { { "D:/051750/freqm/dispselector/dispselector.vhd" "dispselector-arch" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dispselector " "Info: Found entity 1: dispselector" {  } { { "D:/051750/freqm/dispselector/dispselector.vhd" "dispselector" "" { Text "D:/051750/freqm/dispselector/dispselector.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin CLK to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "56 " "Info: Implemented 56 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "25 " "Info: Implemented 25 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "21 " "Info: Implemented 21 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 01 17:02:34 2008 " "Info: Processing ended: Tue Jan 01 17:02:34 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}