📄 dispselector.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY dispselector IS
PORT
(CLK: IN STD_LOGIC;
NUM1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NUM2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NUM3: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NUM4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NUM5: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NUM6: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DIGSGN:out std_logic_vector(0 to 7);
-- DEBUG:out std_logic_vector(3 downto 0);----------debug
CATSEL:out std_logic_vector(0 to 5)
);
END dispselector;
ARCHITECTURE arch OF dispselector IS
SIGNAL DGT : integer range 0 to 9;--要显示的数字
SIGNAL POS : integer range 0 to 5;--数字出现的位置
FUNCTION To_Integer(x:STD_LOGIC_VECTOR(3 downto 0)) RETURN integer IS
BEGIN
case x is
when "0000" => return 0;
when "0001" => return 1;
when "0010" => return 2;
when "0011" => return 3;
when "0100" => return 4;
when "0101" => return 5;
when "0110" => return 6;
when "0111" => return 7;
when "1000" => return 8;
when "1001" => return 9;
when others => return 15;
end case;
END To_Integer;
BEGIN
count6:PROCESS(CLK)
BEGIN
if Rising_edge(CLK) then
if POS>=5 then
POS<=0;
else
POS<=POS+1;
end if;
end if;
END PROCESS count6;
WITH POS SELECT--阴极控制
CATSEL<="011111" WHEN 0,
"101111" WHEN 1,
"110111" WHEN 2,
"111011" WHEN 3,
"111101" WHEN 4,
"111110" WHEN 5;
WITH POS SELECT--选择要显示的数位
DGT<=To_Integer(NUM1) WHEN 0,
To_Integer(NUM2) WHEN 1,
To_Integer(NUM3) WHEN 2,
To_Integer(NUM4) WHEN 3,
To_Integer(NUM5) WHEN 4,
To_Integer(NUM6) WHEN 5;
with DGT select--七段显示信号
DIGSGN<="11111100" when 0,
"01100000" when 1,
"11011010" when 2,
"11110010" when 3,
"01100110" when 4,
"10110110" when 5,
"10111110" when 6,
"11100000" when 7,
"11111110" when 8,
"11110110" when 9,
"00000000" when others;
-- with DGT select----------------------debug
-- DEBUG<="0000" when 0,
-- "0001" when 1,
-- "0010" when 2,
-- "0011" when 3,
-- "0100" when 4,
-- "0101" when 5,
-- "0110" when 6,
-- "0111" when 7,
-- "1000" when 8,
-- "1001" when 9,
-- "1111" when others;
END arch;
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