roycpld.qsf

这是一个verilog HDL 语言的例子

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		RoyCPLD_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY RoyCPLD
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:08:42  JANUARY 20, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_location_assignment PIN_14 -to Clk
set_location_assignment PIN_44 -to Rst
set_location_assignment PIN_100 -to SM_CS1
set_location_assignment PIN_99 -to SM_CS2
set_location_assignment PIN_4 -to SM_db[6]
set_location_assignment PIN_3 -to SM_db[5]
set_location_assignment PIN_5 -to SM_db[4]
set_location_assignment PIN_6 -to SM_db[3]
set_location_assignment PIN_7 -to SM_db[2]
set_location_assignment PIN_1 -to SM_db[1]
set_location_assignment PIN_2 -to SM_db[0]
set_location_assignment PIN_78 -to rs232_rx
set_location_assignment PIN_77 -to rs232_tx
set_location_assignment PIN_21 -to led_d0
set_location_assignment PIN_20 -to led_d1
set_location_assignment PIN_19 -to led_d2
set_location_assignment PIN_18 -to led_d3
set_location_assignment PIN_42 -to bell
set_location_assignment PIN_38 -to sw0
set_location_assignment PIN_39 -to sw1
set_location_assignment PIN_40 -to sw2
set_location_assignment PIN_41 -to sw3
set_global_assignment -name VERILOG_FILE rs232_send_fun.v
set_global_assignment -name VERILOG_FILE RoyCPLD.v
set_global_assignment -name VERILOG_FILE led.v
set_global_assignment -name VERILOG_FILE rs232_speed.v
set_global_assignment -name VERILOG_FILE rs232_rec_fun.v
set_global_assignment -name VERILOG_FILE key.v
set_global_assignment -name FMAX_REQUIREMENT "100 MHz"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON