rs232_rec_fun.v

来自「这是一个verilog HDL 语言的例子」· Verilog 代码 · 共 105 行

`timescale 1ns/1ps

 module rs232_rec_fun
	(
		Clk,Rst,
		band_start,band_CheckFlag,
		rs232_rx_in, RecByte_out,
		Received_Byte_Flag
	);
	
	input Clk;
	input Rst;
	input band_CheckFlag;
	input rs232_rx_in; 
	output Received_Byte_Flag;
	
	output band_start;	
	output wire[7:0]  RecByte_out;
	// Module contents
	
	reg neg_chk0,neg_chk1,neg_chk2,neg_chk3;
	wire neg_chked;
	reg Received_Byte_Flag_r;
	
	always @ ( posedge Clk or negedge Rst ) begin
		if( !Rst) begin
			neg_chk0<=1'b0;
			neg_chk1<=1'b0;
			neg_chk2<=1'b0;
			neg_chk3<=1'b0;
		end
		else begin			
			neg_chk0<=rs232_rx_in;
			neg_chk1<=neg_chk0;
			neg_chk2<=neg_chk1;
			neg_chk3<=neg_chk2;
		end
	end
	
	assign neg_chked = neg_chk3 & neg_chk2 & ~neg_chk1 & ~neg_chk0 ; //  下降沿  1100 //高低电平分别判断两个 
			
	reg band_start_r;
	reg[3:0] num; 
	
	always @ ( posedge Clk or negedge Rst ) begin
		if( !Rst ) begin
			band_start_r <= 1'b0;// 1'bz;//1'b0;
			//num <= 4'd0;  // 在程序中对同一个输出,不能同时在多处赋值 
			Received_Byte_Flag_r <= 'b0;
		end
		else if( neg_chked ) begin
			band_start_r <= 1'b1;
			//num <= 4'd0; 
			Received_Byte_Flag_r <= 'b1;
		end	
		else if ( num == 4'd10) begin
			band_start_r <= 1'b0;// 1'bz;//1'b0;
			//num <= 4'd0; 
			Received_Byte_Flag_r <= 'b0;  // 发送端检测下降沿 10 
		end
	end
	
	assign band_start = band_start_r;
	
	reg [7:0] rec_lastdata_r;
	reg [7:0] rec_tempdata_r;
		
	always @ ( posedge Clk or negedge Rst ) begin
		if( !Rst ) begin
			rec_lastdata_r <=8'h0;
			rec_tempdata_r <=8'h0;
			num <= 4'd0;
			//Received_Byte_Flag_r<='b0;
		end
		else if( Received_Byte_Flag_r ) begin
			if( band_CheckFlag ) begin
				num <= num +1'h1;
				case (num)
					4'd1: rec_tempdata_r[0] <= rs232_rx_in ;
					4'd2: rec_tempdata_r[1] <= rs232_rx_in ;
					4'd3: rec_tempdata_r[2] <= rs232_rx_in ;
					4'd4: rec_tempdata_r[3] <= rs232_rx_in ;
					4'd5: rec_tempdata_r[4] <= rs232_rx_in ;
					4'd6: rec_tempdata_r[5] <= rs232_rx_in ;
					4'd7: rec_tempdata_r[6] <= rs232_rx_in ;
					4'd8: rec_tempdata_r[7] <= rs232_rx_in ; 
					default :;
				endcase
			end
			//rec_lastdata_r <= 8'h21;
		end
		else if (num == 4'd10 ) begin //我们的标准接收模式下只有1+8+1(2)=11bit的有效数据
			num <= 4'd0;
			rec_lastdata_r <= rec_tempdata_r ;
			//Received_Byte_Flag_r <= 'b1;
		end

		//rec_lastdata_r <= 8'h34;
	end
	
	assign RecByte_out = rec_lastdata_r;
	assign Received_Byte_Flag = Received_Byte_Flag_r;

endmodule