roycpld.hif

这是一个verilog HDL 语言的例子

Version 7.0 Build 33 02/05/2007 SJ Full Version
36
1980
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
sm_led
# storage
db|RoyCPLD.(1).cnf
db|RoyCPLD.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
led.v
9b6067b280a0c0957c58462a6ed58f6e
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
seg0
0111111
PARAMETER_UNSIGNED_BIN
DEF
seg1
0000110
PARAMETER_UNSIGNED_BIN
DEF
seg2
1011011
PARAMETER_UNSIGNED_BIN
DEF
seg3
1001111
PARAMETER_UNSIGNED_BIN
DEF
seg4
1100110
PARAMETER_UNSIGNED_BIN
DEF
seg5
1101101
PARAMETER_UNSIGNED_BIN
DEF
seg6
1111101
PARAMETER_UNSIGNED_BIN
DEF
seg7
0000111
PARAMETER_UNSIGNED_BIN
DEF
seg8
1111111
PARAMETER_UNSIGNED_BIN
DEF
seg9
1101111
PARAMETER_UNSIGNED_BIN
DEF
sega
1110111
PARAMETER_UNSIGNED_BIN
DEF
segb
1111100
PARAMETER_UNSIGNED_BIN
DEF
segc
0111001
PARAMETER_UNSIGNED_BIN
DEF
segd
1011110
PARAMETER_UNSIGNED_BIN
DEF
sege
1111001
PARAMETER_UNSIGNED_BIN
DEF
segf
1110001
PARAMETER_UNSIGNED_BIN
DEF
cnt_limit
2000
PARAMETER_SIGNED_DEC
DEF
cnt_limit_by2
1000
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
sm_led:show_sm_led
}
# end
# entity
rs232_band_speed
# storage
db|RoyCPLD.(2).cnf
db|RoyCPLD.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rs232_speed.v
f7888ddb48eb4a3fdfbc44abbc821ce
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
rs232_band_speed:rs232_band_speed_rec
rs232_band_speed:Rs232_band_speed_Send
}
# end
# entity
rs232_rec_fun
# storage
db|RoyCPLD.(3).cnf
db|RoyCPLD.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rs232_rec_fun.v
7a1bb92cbc5d225eea29ad6d091aca
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
rs232_rec_fun:rs232_receiver
}
# end
# entity
rs232_send_fun
# storage
db|RoyCPLD.(4).cnf
db|RoyCPLD.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rs232_send_fun.v
8bb3725df54e358a40c9c9668bc054ec
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
rs232_send_fun:Rs232Sender
}
# end
# entity
key
# storage
db|RoyCPLD.(5).cnf
db|RoyCPLD.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
key.v
38b37a2981d8ad1377b936fe48159a7
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
key:key_check
}
# end
# entity
RoyCPLD
# storage
db|RoyCPLD.(0).cnf
db|RoyCPLD.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RoyCPLD.v
8c36ab374d697fbc6d7c6ee024c4ecf8
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
|
}
# end
# complete