roycpld.fit.qmsg

这是一个verilog HDL 语言的例子

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Info: Fitter can't place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" {  } {  } 0 0 "Fitter can't place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_FITTER_RETRY_TIGHTER_LUT_REG_PACKING" "" "Info: Fitter can't place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" {  } {  } 0 0 "Fitter can't place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Minimize Area " "Info: Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_START" "" "Info: Starting physical synthesis optimizations" {  } {  } 0 0 "Starting physical synthesis optimizations" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "logic and register replication " "Info: Starting physical synthesis algorithm logic and register replication" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "logic and register replication 0 " "Info: Physical synthesis algorithm logic and register replication complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register unpacking " "Info: Starting physical synthesis algorithm register unpacking" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "register unpacking 0 " "Info: Physical synthesis algorithm register unpacking complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_END" "00:00:03 " "Info: Physical synthesis optimizations complete: elapsed time is 00:00:03" {  } {  } 0 0 "Physical synthesis optimizations complete: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:05 " "Info: Fitter placement operations ending: elapsed time is 00:00:05" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.082 ns register register " "Info: Estimated most critical path is register to register delay of 10.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_cnt_r\[3\] 1 REG LAB_X4_Y3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 3; REG Node = 'led_cnt_r\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { led_cnt_r[3] } "NODE_NAME" } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.200 ns) 1.757 ns LessThan0~666 2 COMB LAB_X3_Y3 1 " "Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~666'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.757 ns" { led_cnt_r[3] LessThan0~666 } "NODE_NAME" } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 2.937 ns LessThan0~667 3 COMB LAB_X3_Y3 1 " "Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 2.937 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~667'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~666 LessThan0~667 } "NODE_NAME" } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 4.117 ns LessThan0~668 4 COMB LAB_X3_Y3 1 " "Info: 4: + IC(0.980 ns) + CELL(0.200 ns) = 4.117 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~668'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~667 LessThan0~668 } "NODE_NAME" } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 5.297 ns LessThan0~669 5 COMB LAB_X3_Y3 1 " "Info: 5: + IC(0.980 ns) + CELL(0.200 ns) = 5.297 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~669'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~668 LessThan0~669 } "NODE_NAME" } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 6.477 ns LessThan0~671 6 COMB LAB_X3_Y3 32 " "Info: 6: + IC(0.266 ns) + CELL(0.914 ns) = 6.477 ns; Loc. = LAB_X3_Y3; Fanout = 32; COMB Node = 'LessThan0~671'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~669 LessThan0~671 } "NODE_NAME" } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.845 ns) + CELL(1.760 ns) 10.082 ns led_cnt_r\[22\] 7 REG LAB_X6_Y3 4 " "Info: 7: + IC(1.845 ns) + CELL(1.760 ns) = 10.082 ns; Loc. = LAB_X6_Y3; Fanout = 4; REG Node = 'led_cnt_r\[22\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.605 ns" { LessThan0~671 led_cnt_r[22] } "NODE_NAME" } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.474 ns ( 34.46 % ) " "Info: Total cell delay = 3.474 ns ( 34.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.608 ns ( 65.54 % ) " "Info: Total interconnect delay = 6.608 ns ( 65.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.082 ns" { led_cnt_r[3] LessThan0~666 LessThan0~667 LessThan0~668 LessThan0~669 LessThan0~671 led_cnt_r[22] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 13 " "Info: Average interconnect usage is 13% of the available device resources. Peak interconnect usage is 13%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Allocated 156 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 06 14:49:00 2009 " "Info: Processing ended: Fri Feb 06 14:49:00 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/CPLD Prj/RoyCPLD/RoyCPLD.fit.smsg " "Info: Generated suppressed messages file D:/CPLD Prj/RoyCPLD/RoyCPLD.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}